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56f8000 16-bit digital signal controllers freescale.com 56f8023 data sheet preliminary technical data mc56f8023 rev. 3 01/2007
56f8023 data sheet, rev. 3 2 freescale semiconductor preliminary document revision history version history description of change rev. 0 initial public release. rev. 1 ? in table 10-4 , added an entry for flash data retention with less than 100 program/erase cycles (minimum 20 years). ?in table 10-6 , changed the device clock speed in stop mode from 8mhz to 4mhz. ?in table 10-12 , changed the typical relaxation oscillator output frequency in standby mode from 400khz to 200khz. ? changed input propagation delay values in table 10-20 as follows: old values: 1 s typical, 2 s maximum new values: 35 ns typical, 45 ns maximum rev. 2 in table 10-19 , changed the maximum adc internal clock frequency from 8 mhz to 5.33 mhz. rev. 3 ? added the following note to the description of the tms signal in table 2-3 : note: always tie the tms pin to v dd through a 2.2k resistor. ? corrected pin number labels in figure 11-1 as follows: old labels: pin 1, pin 12, pin 23, pin 34 new labels: pin 1, pin 9, pin 17, pin 25 please see http://www.freescale.com for the most current data sheet revision.
56f8023 data sheet, rev. 3 freescale semiconductor 3 preliminary 56f8023 block diagram programmable interval timer program controller and hardware looping unit data alu 16 x 16 + 36 -> 36-bit mac three 16-bit input registers four 36-bit accumulators address generation unit bit manipulation unit 16-bit 56800e core interrupt controller 4 unified data / program ram 2k x 16 pdb pdb xab1 xab2 xdb2 cdbr qspi or pwm or i 2 c or tmra or gpiob ipbus bridge (ipbb) system bus control r/w control memory pab pab cdbw cdbr cdbw jtag/eonce port or gpiod digital reg analog reg low-voltage supervisor v cap v dd v ss v dda v ssa 4 reset or gpioa ad0 4 clock generator* system integration module p o r o s c pwm or tmra or gpioa *includes on-chip relaxation oscillator cop/ watchdog ad1 4 program memory 16k x 16 flash adc or cmp or gpioc qsci or pwm or i 2 c or tmra or gpiob 2 2 i 2 c or cmp or gpiob 2 5 dac ? up to 32 mips at 32mhz core frequency ? dsp and mcu functionality in a unified, c-efficient architecture ? 32kb (16k x 16) program flash ? 4kb (2k x 16) unified data/program ram ? one 6-channel pwm module ? two 3-channel 12-bit analog-to-digital converters (adcs) ? two internal 12-bit digital-to-analog converters (dacs) ? two analog comparators ? one programmable interval timer (pit) ? one queued serial comm unication interface (qsci) with lin slave functionality ? one queued serial peri pheral interfaces (qspi) ? one 16-bit quad timer ? one inter-integrated circuit (i 2 c) port ? computer operating properly (cop)/watchdog ? on-chip relaxation oscillator ? integrated power-on reset (por) and low-voltage interrupt (lvi) module ? jtag/enhanced on-chip emulation (once?) for unobtrusive, real-time debugging ? up to 26 gpio lines ? 32-pin lqfp package 56f8023 general description
56f8023 data sheet, rev. 3 4 freescale semiconductor preliminary part 1: overview . . . . . . . . . . . . . . . . . . . . . . . 5 1.1. 56f8023 features . . . . . . . . . . . . . . . . . . . . . 5 1.2. 56f8023 description . . . . . . . . . . . . . . . . . . . 7 1.3. award-winning development environment . . 8 1.4. architecture block diagram . . . . . . . . . . . . . 8 1.5. product documentation . . . . . . . . . . . . . . . . 16 1.6. data sheet conventions. . . . . . . . . . . . . . . 16 part 2: signal/connection descriptions . . 17 2.1. introduction . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.2. 56f8023 signal pins . . . . . . . . . . . . . . . . . . 21 part 3: occs . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.1. overview. . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.2. features . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.3. operating modes . . . . . . . . . . . . . . . . . . . . . 30 3.4. internal clock source . . . . . . . . . . . . . . . . . 31 3.5. crystal oscillator. . . . . . . . . . . . . . . . . . . . . 31 3.6. ceramic resonator. . . . . . . . . . . . . . . . . . . 32 3.7. external clock input - crystal oscillator option . . . . . . . . . . . . . . 32 3.8. alternate external clock input . . . . . . . . . . 33 part 4: memory maps . . . . . . . . . . . . . . . . . . 33 4.1. introduction . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.2. interrupt vector table . . . . . . . . . . . . . . . . . 34 4.3. program map . . . . . . . . . . . . . . . . . . . . . . . 36 4.4. data map . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.5. eonce memory map . . . . . . . . . . . . . . . . . . 37 4.6. peripheral memory-mapped registers . . . . 38 part 5: interrupt controller (itcn) . . . . . . . 51 5.1. introduction . . . . . . . . . . . . . . . . . . . . . . . . . 51 5.2. features . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 5.3. functional description . . . . . . . . . . . . . . . . 52 5.4. block diagram . . . . . . . . . . . . . . . . . . . . . . . 54 5.5. operating modes . . . . . . . . . . . . . . . . . . . . 54 5.6. register descriptions . . . . . . . . . . . . . . . . . . 54 5.7. resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 part 6: system integration module (sim). . 74 6.1. introduction . . . . . . . . . . . . . . . . . . . . . . . . . 74 6.2. features . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 6.3. register descriptions . . . . . . . . . . . . . . . . . 75 6.4. clock generation overview . . . . . . . . . . . . 99 6.5. power-saving modes . . . . . . . . . . . . . . . . 100 6.6. resets . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 6.7. clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 6.8. interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 104 part 7: security features . . . . . . . . . . . . . 104 7.1. operation with security enabled . . . . . . . . 104 7.2. flash access lock and unlock mechanisms . . . . . . . . . . 105 part 8: general-purpose input/output (gpio) . . . . . . . . . . . . . . . . . . . . . . . 106 8.1. introduction . . . . . . . . . . . . . . . . . . . . . . . . 106 8.2. configuration . . . . . . . . . . . . . . . . . . . . . . . 106 8.3. reset values . . . . . . . . . . . . . . . . . . . . . . . 108 part 9: joint test action group (jtag) . .113 9.1. 56f8023 information . . . . . . . . . . . . . . . . . 113 part 10: specifications. . . . . . . . . . . . . . . . 113 10.1. general characteristics . . . . . . . . . . . . . . 113 10.2. dc electrical characteristics . . . . . . . . . . 117 10.3. ac electrical characteristics . . . . . . . . . . 120 10.4. flash memory characteristics . . . . . . . . . 121 10.5. external clock operation timing . . . . . . . 121 10.6. phase locked loop timing . . . . . . . . . . . 122 10.7. relaxation oscillator timing. . . . . . . . . . . 122 10.8. reset, stop, wait, mode select, and interrupt timing. . . . . . . . . . . 124 10.9. serial peripheral interface (spi) timing . 125 10.10. quad timer timing . . . . . . . . . . . . . . . . 128 10.11. serial communication interface (sci) timing. . . . . . . . . . . . . . . . . 129 10.12. inter-integrated circuit interface (i2c) timing . . . . . . . . . . . . . . . . . 130 10.13. jtag timing . . . . . . . . . . . . . . . . . . . . . 131 10.14. analog-to-digital converter (adc) parameters . . . . . . . . . . . . 133 10.15. equivalent circuit for adc inputs . . . . . . 134 10.16. comparator (cmp) parameters . . . . . . . 134 10.17. digital-to-analog converter (dac) parameters . . . . . . . . . . . . 135 10.18. power consumption . . . . . . . . . . . . . . . 136 part 11: packaging . . . . . . . . . . . . . . . . . . . 138 11.1. 56f8023 package and pin-out information . . . . . . . . . . . 138 part 12: design considerations . . . . . . . . .141 12.1. thermal design considerations . . . . . . . . 141 12.2. electrical design considerations . . . . . . . 142 part 13: ordering information . . . . . . . . . . 143 part 14: appendix. . . . . . . . . . . . . . . . . . . . 144 56f8023 data sheet table of contents
56f8023 features 56f8023 data sheet, rev. 3 freescale semiconductor 5 preliminary part 1 overview 1.1 56f8023 features 1.1.1 digital signal controller core ? efficient 16-bit 56800e family digital signal cont roller (dsc) engine with dual harvard architecture ? as many as 32 million instructions pe r second (mips) at 32mhz core frequency ? single-cycle 16 16-bit parallel multiplier-accumulator (mac) ? four 36-bit accumulators, including extension bits ? 32-bit arithmetic and logic multi-bit shifter ? parallel instruction set with unique dsp addressing modes ? hardware do and rep loops ? three internal address buses ? four internal data buses ? instruction set supports both dsp and controller functions ? controller-style addressing modes and instructions for compact code ? efficient c compiler and local variable support ? software subroutine and interrupt stac k with depth limited only by memory ? jtag/enhanced on-chip emulation (once) for unobtrusive, processor speed-independent, real-time debugging 1.1.2 memory ? dual harvard architecture permits as many as thre e simultaneous accesses to program and data memory ? flash security and protection that prevent unauth orized users from gaining access to the internal flash ?on-chip memory ? 32kb of program flash ? 4kb of unified data/program ram ? eeprom emulation capability using flash 1.1.3 peripheral circuits for 56f8023 ? one multi-function six-output pu lse width modulator (pwm) module ? up to 96mhz pwm operating clock ? 15 bits of resolution ? center-aligned and edge-aligned pwm signal mode ? four programmable fault inputs with programmable digital filter ? double-buffered pwm registers ? each complementary pwm signal pair allows selection of a pwm supply source from: ?pwm generator
56f8023 data sheet, rev. 3 6 freescale semiconductor preliminary ?external gpio ? internal timers ? analog comparator outputs ? adc conversion result which compares with valu es of adc high- and low-limit registers to set pwm output ? two independent 12-bit analog-to-digital converters (adcs) ? 2 x 3 channel inputs ? supports both simultaneous and sequential conversions ? adc conversions can be synchronized by both pwm and timer modules ? sampling rate up to 2.67msps ? 16-word result buffer registers ? two internal 12-bit digital-to-analog converters (dacs) ?2 s settling time when output swing from rail to rail ? automatic waveform generation generates sq uare, triangle and sawtooth waveforms with programmable period, update rate, and range ? one 16-bit multi-purpose quad timer module (tmr) ? up to 96mhz operating clock ? eight independent 16-bit counter/ timers with cascading capability ? each timer has capture and compare capability ? up to 12 operating modes ? one queued serial communication inte rface (qsci) with lin slave functionality ? full-duplex or single-wire operation ? two receiver wake-up methods: ? idle line ? address mark ? four-bytes-deep fifos are availabl e on both transmitter and receiver ? one queued serial peripheral interfaces (qspi) ? full-duplex operation ? master and slave modes ? four-words-deep fifos available on both transmitter and receiver ? programmable length transactions (2 to 16 bits) ? one inter-integrated circuit (i 2 c) port ? operates up to 400kbps ? supports both master and slave operation ? supports both 10-bit address mode and broadcasting mode ? one 16-bit programmable interval timer (pit) ? two analog comparators (cmps)
56f8023 description 56f8023 data sheet, rev. 3 freescale semiconductor 7 preliminary ? selectable input source includes external pins, dacs ? programmable output polarity ? output can drive timer input, pw m fault input, pwm source, extern al pin output and trigger adcs ? output falling and rising edge det ection able to generate interrupts ? computer operating properly (cop)/watchdog tim er capable of selecting different clock sources ? up to 26 general-purpose i/o (g pio) pins with 5v tolerance ? integrated power-on reset an d low-voltage interrupt module ? phase lock loop (pll) provides a high-sp eed clock to the co re and peripherals ? clock sources: ? on-chip relaxation oscillator ? external clock: crystal oscillator, ceram ic resonator, and external clock source ? jtag/eonce debug programming in terface for real-time debugging 1.1.4 energy information ? fabricated in high-density cmos with 5v tolerance ? on-chip regulators for digital and analog circuitry to lower cost and reduce noise ? wait and stop modes available ? adc smart power management ? each peripheral can be indivi dually disabled to save power 1.2 56f8023 description the 56f8023 is a member of the 56800e core-based family of digital signal cont rollers (dscs). it combines, on a single chip, the processing power of a dsp and the functionality of a microcontroller with a flexible set of peripherals to create an extremely cost-effective solution. because of its low cost, configuration flexibility, and comp act program code, the 56f8023 is we ll-suited for many applications. the 56f8023 includes many peripherals that are especially useful for industrial control, motion control, home appliances, general-purpose inve rters, smart sensors, fire and security systems, switched-mode power supply, power management, and medical monitoring applications. the 56800e core is based on a dual harvard-style architecture consisting of three execution units operating in parallel, allowing as many as six operations per inst ruction cycle. the mcu-style programming model and optimized instru ction set allow straightforward ge neration of efficient, compact dsp and control code. the instruction set is also highly efficient for c compilers to enable rapid development of optimized control applications. the 56f8023 supports program executio n from internal memories. two data operands can be accessed from the on-chip data ram per instruction cycle. the 56f8023 also offers up to 26 general-purpose input/output (gpio) lines, depe nding on peripheral configuration. the 56f8023 digital signal controll er includes 32kb of progra m flash and 4kb of unified data/program ram. program flash memory can be independently bulk erased or erased in pages.
56f8023 data sheet, rev. 3 8 freescale semiconductor preliminary program flash page erase size is 512 bytes (256 words). 1.3 award-winning development environment processor expert tm (pe) provides a rapid application design (rad) tool that combines easy-to-use component-based software application cr eation with an expert knowledge system. the codewarrior integrated devel opment environment is a sophisti cated tool for code navigation, compiling, and debugging. a complete set of evaluation modules (evms) , demonstration board kit and development system cards will s upport concurrent engin eering. together, pe, codewarrior and evms create a complete, scalable tools solution for easy, fast, and efficient development. a full set of programmable periphe rals ? pwm, adcs, qsci, qspi, i2 c, pit, quad timers, dacs, and analog comparators ? supports various applications. ea ch peripheral can be independently shut down to save power. any pin in these peripherals can also be used as general pur pose input/outputs (gpios). 1.4 architecture block diagram the 56f8023?s architecture is shown in figures 1-1 , 1-2 , 1-3 , 1-4 , 1-5 , 1-6 , and 1-7 . figure 1-1 illustrates how the 56800e system buses communicat e with internal memories and th e ipbus bridge and the internal connections between each unit of the 56800e core. figure 1-2 shows the peripherals and control blocks connected to the ipbus bridge. figures 1-3 , 1-4 , 1-5 , 1-6 , and 1-7 detail how the device?s i/o pins are muxed. the figures do not show the on-board regul ator and power and gro und signals. please see part 2, signal/connection descriptions , for information about which signals are multiplexed with those of other peripherals. 1.4.1 pwm, tmr and adc connections figure 1-3 shows the over- and under-voltage connections from the adc to the pwm and the connections to the pwm from the tmr and gpio . these signals can control the pwm outputs in a similar manner to the over- and under-voltage control signals. see the 56f802x and 56f803x peripheral reference manual for additional information. the pwm_reload_sync output can be connected to the timer?s channel 3 input and the timer?s channels 2 and 3 outputs are connected to the adc sync input s. timer channel 3 output is connected to sync0 and timer channel 2 is connected to sync1. these are controlled by bi ts in the sim control register; see section 6.3.1 .
architecture block diagram 56f8023 data sheet, rev. 3 freescale semiconductor 9 preliminary figure 1-1 56800e core block diagram data dsp56800e core arithmetic logic unit (alu) xab2 pab pdb cdbw cdbr xdb2 program memory data / ipbus interface bit- manipulation unit n3 m01 address xab1 generation unit (agu) pc la la2 hws0 hws1 fira omr sr fisr lc lc2 instruction decoder interrupt unit looping unit program control unit alu1 alu2 mac and alu a1 a2 a0 b1 b2 b0 c1 c2 c0 d1 d2 d0 y1 y0 x0 enhanced jtag tap r2 r3 r4 r5 sp r0 r1 n y multi-bit shifter once? program ram
56f8023 data sheet, rev. 3 10 freescale semiconductor preliminary figure 1-2 peripheral subsystem ipbus gpio a interrupt controller to/from ipbus bridge gpio b gpio c occs (rosc / pll / osc) por & lvi sim gpio d low-voltage interrupt system por cop reset rese t (muxed with gpioa7) cop (continues on figure 1-3 )
architecture block diagram 56f8023 data sheet, rev. 3 freescale semiconductor 11 preliminary figure 1-3 56f8023 i/o pi n-out muxing (part 1/5) to/from ipbus bridge ipbus dac sync on figure 1-5 intc pit0 sync sync0, sync1 3 sync0, sync1 on figure 1-7 limit on figure 1-6 over/under limits ana1 anb1 adc gpioc1 gpioc5 ana0 ana0 on figure 1-5 ana2 (v refha ) gpioc2 anb0 anb0 on figure 1-5 anb2 (v refhb ) gpioc6 2
56f8023 data sheet, rev. 3 12 freescale semiconductor preliminary figure 1-4 56f8023 i/o pi n-out muxing (part 2/5) to/from ipbus bridge ipbus gpiob4 qsci0 qspi0 i 2 c clko 2 2 rxd0, txd0 ta2, ta3 on figure 1-7 miso0, mosi0 2 2 sclk0, ss0 scl, sda 2 2 gpiob6 - 7 gpiob2 - 3 gpiob0 - 1 ta0 on figure 1-7
architecture block diagram 56f8023 data sheet, rev. 3 freescale semiconductor 13 preliminary figure 1-5 56f8023 i/o pi n-out muxing (part 3/5) to/from ipbus bridge ipbus dac0 gpioc0 gpioc4 cmpa cmp_in3 export import cmpai3 cmpbi3 cmpb cmp_in3 export import ta0o, ta1o on figure 1-7 reload on figure 1-6 cmp_out anb0 on figure 1-3 cmp_out cmpbo on figure 1-6 , figure 1-7 ana0 on figure 1-3 cmpao on figure 1-6 , figure 1-7 dac1 dac sync on figure 1-3 2
56f8023 data sheet, rev. 3 14 freescale semiconductor preliminary figure 1-6 56f8023 i/o pi n-out muxing (part 4/5) to/from ipbus bridge ipbus gpioa6 ta0 on figure 1-7 ta2 - 3 on figure 1-7 gpioa0 - 3 pwm pwm0 - 3 fault0 pwma4 - 5 fault1 reload psrc0 - 2 gpioa4 - 5 fault2 fault3 reload on figure 1-7 , figure 1-5 2 4 2 2 1 1 gpiob5 ta1 on figure 1-7 3 3 3 gpiob2 - 4 on figure 1-4 limit on figure 1-3 ta0o, ta2o, ta3o on figure 1-3 cmpao on figure 1-5 cmpbo on figure 1-5 3
architecture block diagram 56f8023 data sheet, rev. 3 freescale semiconductor 15 preliminary figure 1-7 56f8023 i/o pi n-out muxing (part 5/5) to/from ipbus bridge ipbus tmra t0o t0i t1o t1i t2o t2i t3o t3i ta0o on figure 1-6 (pwm) ta0 on figure 1-6 (gpioa6) ta0 on figure 1-4 (gpiob4) ta1 on figure 1-6 (gpiob5) cmpao on figure 1-6 (cmpa) sync1 on figure 1-3 (adc) ta2o on figure 1-6 (pwm) ta2 on figure 1-6 (gpioa4) ta2 on figure 1-4 (gpiob2) cmpbo on figure 1-6 (cmpb) sync0 on figure 1-3 (adc) ta3o on figure 1-6 (pwm) ta3 on figure 1-6 (gpioa5) ta3 on figure 1-4 (gpiob3) reload on figure 1-6 (pwm)
56f8023 data sheet, rev. 3 16 freescale semiconductor preliminary 1.5 product documentation the documents listed in table 1-1 are required for a complete description and proper design with the 56f8023. documentation is available from local freescale distributors, freescale se miconductor sales offices, freescale literature distribut ion centers, or online at: http://www.freescale.com table 1-1 56f8023 chip documentation 1.6 data sheet conventions this data sheet uses the following conventions: topic description order number dsp56800e reference manual detailed description of the 56800e family architecture, 16-bit digital signal controller core processor, and the instruction set dsp56800erm 56f802x and 56f803x peripheral reference manual detailed description of peripherals of the 56f802x and 56f803x family of devices mc56f80xxrm 56f802x and 56f803x serial bootloader user guide detailed description of the serial bootloader in the 56f802x and 56f803x family of devices 56f80xxblug 56f8023 technical data sheet electrical and timing specifications, pin descriptions, and package descriptions (this document) mc56f8023 56f8023 errata details any chip issues that might be present mc56f8023e overbar this is used to indicate a signal that is active when pulled low. for example, the reset pin is active when low. ?asserted? a high true (active high) signal is hi gh or a low true (active low) signal is low. ?deasserted? a high true (active high) signal is low or a low true (active low) signal is high. examples: signal/symbol logic state signal state voltage 1 1. values for v il , v ol , v ih , and v oh are defined by individual product specifications. pin true asserted v il /v ol pin false deasserted v ih /v oh pin true asserted v ih /v oh pin false deasserted v il /v ol
introduction 56f8023 data sheet, rev. 3 freescale semiconductor 17 preliminary part 2 signal/connection descriptions 2.1 introduction the input and output signals of the 56f8023 are orga nized into functional groups, as detailed in table 2-1 . table 2-2 summarizes all device pins. in table 2-2 , each table row describes th e signal or signals present on a pin, sorted by pin number. table 2-1 functional gr oup pin allocations functional group number of pins power inputs (v dd , v dda )2 ground (v ss , v ssa )3 supply capacitors 1 reset 1 1. pins may be shared with other peripherals. see table 2-2 . 1 pulse width modulator (pwm) ports 1 11 serial peripheral interface (spi) ports 1 4 timer module a (tmra) ports 1 4 analog-to-digital converter (adc) ports 1 6 serial communications interface 0 (sci0) ports 1 2 inter-integrated circuit interface (i 2 c) ports 1 2 jtag/enhanced on-chip emulation (eonce 1 ) 4
56f8023 data sheet, rev. 3 18 freescale semiconductor preliminary in table 2-2 , peripheral pins in bold identify reset state. table 2-2 56f8023 pins peripherals: pin # pin name signal name gpio i2c qsci qspi adc pwm quad timer comp power & ground jtag misc. 1 gpiob6 gpiob6, rxd0, sda, clkin b6 sda rxd0 clkin 2 gpiob1 gpiob1, ss0 , sda b1 sda ss0 3 gpiob7 gpiob7, txd0, scl b7 scl txd0 4 gpiob5 gpiob5, ta1, fault3, clkin b5 fault3 ta1 clkin 5 gpioc4 gpioc4, anb0 & cmpbi3 c4 anb0 cmpbi3 6 gpioc5 gpioc5, anb1 c5 anb1 7 gpioc6 gpioc6, anb2, v refhb c6 anb2 v refhb 8 vdda v dda v dda 9 vssa v ssa v ssa 10 gpioc2 gpioc2, ana2, v refha c2 ana2 v refha 11 gpioc1 gpioc1, ana1 c1 ana1 12 gpioc0 gpioc0, ana0 & cmpai3 c0 ana0 cmpai3 13 vss v ss v ss 14 tck tck, gpiod2 d2 tck 15 reset reset , gpioa7 a7 reset 16 gpiob3 gpiob3, mosi0, ta3, psrc1 b3 mosi0 psrc1 ta3 17 gpiob2 gpiob2, miso0, ta2, psrc0 b2 miso0 psrc0 ta2 18 gpioa6 gpioa6, fault0, ta0 a6 fault0 ta0 19 gpiob4 gpiob4, ta0, clko, psrc2 b4 psrc2 ta0 clko 20 gpioa5 gpioa5, pwm5, ta3, fault2 a5 pwm5 fault2 ta3 21 gpiob0 gpiob0, sclk0, scl b0 scl sclk0 22 gpioa4 gpioa4, pwm4, ta2, fault1 a4 pwm4 fault1 ta2 23 gpioa2 gpioa2, pwm2 a2 pwm2 24 gpioa3 gpioa3, pwm3 a3 pwm3 25 vcap v cap v cap 26 vdd v dd v dd 27 vss v ss v ss 28 gpioa1 gpioa1, pwm1 a1 pwm1
introduction 56f8023 data sheet, rev. 3 freescale semiconductor 19 preliminary 29 gpioa0 gpioa0, pwm0 a0 pwm0 30 tdi tdi, gpiod0 d0 td1 31 tms tms, gpiod3 d3 tms 32 tdo tdo, gpiod1 d1 tdo table 2-2 56f8023 pins (continued) peripherals: pin # pin name signal name gpio i2c qsci qspi adc pwm quad timer comp power & ground jtag misc.
56f8023 data sheet, rev. 3 20 freescale semiconductor preliminary figure 2-1 56f8023 signals identified by functional group v dd v dda v ssa other supply ports jtag/ eonce or gpiod 1 1 2 v cap 1 tck (gpiod2) tms (gpiod3) gpioc2 (ana2, v refha ) 1 1 1 56f8023 1 tdi (gpiod0) tdo (gpiod1) gpiob5 (ta1, fault3, clkin) gpiob6 (rxd0, sda, clkin) gpiob7 (txd0, scl) 1 1 1 v ss power ground power ground gpioc1 (ana1) 1 gpioc0 (ana0 & cmpai3) 1 reset or gpioa reset (gpioa7) 1 gpiob0 (sclk0, scl) gpiob1 (ss0 , sda) spi or i 2 c or pwm or tmra or gpiob 1 1 sci or pwm or i 2 c or tmra or spi or gpiob adc or cmp or gpioc gpiob2 (miso0, ta2, psrc0) gpiob3 (mosi0, ta3, psrc1) 1 1 gpioa0-3 (pwm0-3) gpioa4 (pwm4, ta2, fault1) gpioa5 (pwm5, ta3, fault2) 4 1 1 gpioa6 (fault0, ta0) 1 pwm or tmra or gpioa 1 1 1 gpioc6 (anb2, v refhb ) 1 gpioc5 (anb1) 1 gpioc4 (anb0 & cmpbi3) 1 gpiob4 (ta0, psrc2, clko) 1
56f8023 signal pins 56f8023 data sheet, rev. 3 freescale semiconductor 21 preliminary 2.2 56f8023 signal pins after reset, each pin is configured for its primary function (listed first). any alternate functionality must be programmed. table 2-3 56f8023 signal and package information for the 32-pin lqfp signal name lqfp pin no. type state during reset signal description v dd 26 supply supply i/o power ? this pin supplies 3.3v power to the chip i/o interface. v ss 13 supply supply v ss ? these pins provide ground fo r chip logic and i/o drivers. v ss 27 v dda 8 supply supply adc power ? this pin supplies 3.3v power to the adc modules. it must be connected to a clean analog power supply. v ssa 9 supply supply adc analog ground ? this pin supplies an analog ground to the adc modules. v cap 25 supply supply v cap ? connect this pin to a 4.7 f or greater bypass capacitor in order to bypass the core voltage regulator, required for proper chip operation. see section 10.2.1 . reset (gpioa7) 15 input input/open drain output input, internal pull-up enabled reset ? this input is a direct hardware reset on the processor. when reset is asserted low, the chip is initialized and placed in the reset state. a schmitt trigger input is used for noise immunity. the internal reset signal will be deasserted synchronous with the internal clocks after a fixed numbe r of internal clocks. port a gpio ? this gpio pin can be individually programmed as an input or open dr ain output pin. note that reset functionality is disabled in this mode and the chip can only be reset via por, cop reset, or software reset. after reset, the default state is reset . gpioa0 (pwm0) 29 input/ output output input, internal pull-up enabled port a gpio ? this gpio pin can be individually programmed as an input or output pin. pwm0 ? this is one of the six pwm output pins. after reset, the default state is gpioa0. return to table 2-2
56f8023 data sheet, rev. 3 22 freescale semiconductor preliminary gpioa1 (pwm1) 28 input/ output output input, internal pull-up enabled port a gpio ? this gpio pin can be individually programmed as an input or output pin. pwm1 ? this is one of the six pwm output pins. after reset, the default state is gpioa1. gpioa2 (pwm2) 23 input/ output output input, internal pull-up enabled port a gpio ? this gpio pin can be individually programmed as an input or output pin. pwm2 ? this is one of the six pwm output pins. after reset, the default state is gpioa2. gpioa3 (pwm3) 24 input/ output output input, internal pull-up enabled port a gpio ? this gpio pin can be individually programmed as an input or output pin. pwm3 ? this is one of the six pwm output pins. after reset, the default state is gpioa3. gpioa4 (pwm4) (ta2 1 ) (fault1 2 ) 22 input/ output output input/ output input input, internal pull-up enabled port a gpio ? this gpio pin can be individually programmed as an input or output pin. pwm4 ? this is one of the six pwm output pins. ta2 ? timer a, channel 2 fault1 ? this fault input pin is used for disabling selected pwm outputs in cases where fault conditions originate off-chip. after reset, the default state is gp ioa4. the peripheral functionality is controlled via the sim. see section 6.3.16 . 1 the ta2 signal is also brought out on the gpiob2-3 pin. 2 the fault1 signal is also brought out on the gpiob4 pin. return to table 2-2 table 2-3 56f8023 signal and package information for th e 32-pin lqfp (continued) signal name lqfp pin no. type state during reset signal description
56f8023 signal pins 56f8023 data sheet, rev. 3 freescale semiconductor 23 preliminary gpioa5 (pwm5) (ta3 3 ) (fault2 4 ) 20 input/ output output input/ output input input, internal pull-up enabled port a gpio ? this gpio pin can be individually programmed as an input or output pin. pwm5 ? this is one of the six pwm output pins. ta3 ? timer a, channel 3 fault2 ? this fault input pin is used for disabling selected pwm outputs in cases where fault conditions originate off-chip. after reset, the default state is gp ioa5. the peripheral functionality is controlled via the sim. see section 6.3.16 . 3 the ta3 signal is also brought out on the gpiob2-3 pin. 4 the fault2 signal is also brought out on the gpiob4 pin. gpioa6 (fault0) (ta0 5 ) 18 input/ output input input, internal pull-up enabled port a gpio ? this gpio pin can be individually programmed as an input or output pin. fault0 ? this fault input pin is used for disabling selected pwm outputs in cases where fault conditions originate off-chip. ta0 ? timer a, channel 0. after reset, the default state is gp ioa6. the peripheral functionality is controlled via the sim. see section 6.3.16 . 5 the ta0 signal is also brought out on the gpiob4 pin. return to table 2-2 table 2-3 56f8023 signal and package information for th e 32-pin lqfp (continued) signal name lqfp pin no. type state during reset signal description
56f8023 data sheet, rev. 3 24 freescale semiconductor preliminary gpiob0 (sclk0) (scl 6 ) 21 input/ output input/ output input/ output input, internal pull-up enabled port b gpio ? this gpio pin can be individually programmed as an input or output pin. qspi0 serial clock ? in the master mode, this pin serves as an output, clocking slaved listeners. in slave mode, this pin serves as the data clock input. a schmitt trigger input is used for noise immunity. serial clock ? this pin serves as the i 2 c serial clock. after reset, the default state is gp iob0. the peripheral functionality is controlled via the sim. see section 6.3.16 . 6 the scl signal is also brought out on the gpiob7 pin. gpiob1 (ss0 ) (sda 7 ) 2 input/ output input/ output input input, internal pull-up enabled port b gpio ? this gpio pin can be individually programmed as an input or output pin. qspi0 slave select ? ss is used in slave mode to indicate to the qspi0 module that the current transfer is to be received. serial data ? this pin serves as the i 2 c serial data line. after reset, the default state is gp iob1. the peripheral functionality is controlled via the sim. see section 6.3.16 . 7 the sda signal is also brought out on the gpiob6 pin. return to table 2-2 table 2-3 56f8023 signal and package information for th e 32-pin lqfp (continued) signal name lqfp pin no. type state during reset signal description
56f8023 signal pins 56f8023 data sheet, rev. 3 freescale semiconductor 25 preliminary gpiob2 (miso0) (ta2 8 ) (psrc0) 17 input/ output input/ output input/ output input input, internal pull-up enabled port b gpio ? this gpio pin can be individually programmed as an input or output pin. qspi0 master in/slave out ? this serial data pin is an input to a master device and an output from a slave device. the miso line of a slave device is placed in the high-im pedance state if the slave device is not selected. the slave device places data on the miso line a half-cycle before the cloc k edge the master device uses to latch the data. ta2 ? timer a, channel 2 psrc0 ? external pwm signal source input for the complementary pwm4/pwm5 pair. after reset, the default state is gp iob2. the peripheral functionality is controlled via the sim. see section 6.3.16 . 8 the ta2 signal is also brought out on the gpioa4 pin. gpiob3 (mosi0) (ta3 9 ) (psrc1) 16 input/ output input/ output input/ output input input, internal pull-up enabled port b gpio ? this gpio pin can be individually programmed as an input or output pin. qspi0 master out/slave in ? this serial data pin is an output from a master device and an input to a slave device. the master device places data on the mosi line a half-cycle before t he clock edge the slave device uses to latch the data. ta3 ? timer a, channel 3 psrc1 ? external pwm signal source input for the complementary pwm2/pwm3 pair. after reset, the default state is gp iob3. the peripheral functionality is controlled via the sim. see section 6.3.16 . 9 the ta3 signal is also brought out on the gpioa5 pin. return to table 2-2 table 2-3 56f8023 signal and package information for th e 32-pin lqfp (continued) signal name lqfp pin no. type state during reset signal description
56f8023 data sheet, rev. 3 26 freescale semiconductor preliminary gpiob4 (ta0 10 ) (psrc2) (clko) 19 input/ output input/ output input output input, internal pull-up enabled port b gpio ? this gpio pin can be individually programmed as an input or output pin. ta0 ? timer a, channel 0 psrc2 ? external pwm signal source input for the complementary pwm0/pwm1 pair. clock output ? this is a buffered clock out put; the clock source is selected by clockout select (clkosel) bits in the clock output select register (clkout). see section 6.3.7 . after reset, the default state is gp iob4. the peripheral functionality is controlled via the sim. see section 6.3.16 . 10 the ta0 signal is also brought out on the gpiob4 and gpioa6 pins. gpiob5 (ta1) (fault3) (clkin) 4 input/ output input/ output input input input, internal pull-up enabled port b gpio ? this gpio pin can be individually programmed as an input or output pin. ta1 ? timer a, channel 1 fault3 ? this fault input pin is used for disabling selected pwm outputs in cases where fault conditions originate off-chip. external clock input ? this pin serves as an external clock input. after reset, the default state is gp iob5. the peripheral functionality is controlled via the sim. see section 6.3.16 . return to table 2-2 table 2-3 56f8023 signal and package information for th e 32-pin lqfp (continued) signal name lqfp pin no. type state during reset signal description
56f8023 signal pins 56f8023 data sheet, rev. 3 freescale semiconductor 27 preliminary gpiob6 (rxd0) (sda 11 ) (clkin) 1 input/ output input input/ output input input, internal pull-up enabled port b gpio ? this gpio pin can be individually programmed as an input or output pin. receive data 0 ? qsci0 receive data input. serial data ? this pin serves as the i 2 c serial data line. external clock input ? this pin serves as an external clock input. after reset, the default state is gp iob6. the peripheral functionality is controlled via the sim (see section 6.3.16 ) and the clkmode bit of the occs oscillator control register. 11 the sda signal is also brought out on the gpiob1 pin. gpiob7 (txd0) (scl 12 ) 3 input/ output input/ output input/ output input, internal pull-up enabled port b gpio ? this gpio pin can be individually programmed as an input or output pin. transmit data 0 ? qsci0 transmit data output or transmit/receive in single wire operation. serial clock ? this pin serves as the i 2 c serial clock. after reset, the default state is gp iob7. the peripheral functionality is controlled via the sim. see section 6.3.16 . 12 the scl signal is also brought out on the gpiob0 pin. gpioc0 (ana0 & cmpai3) 12 input/ output analog input input port c gpio ? this gpio pin can be individually programmed as an input or output pin. ana0 ? analog input to adc a, channel 0. comparator a, input 3 ? this is an analog input to comparator a. when used as an analog input, the signal goes to both the ana0 and cmpai3. after reset, the default state is gpioc0. return to table 2-2 table 2-3 56f8023 signal and package information for th e 32-pin lqfp (continued) signal name lqfp pin no. type state during reset signal description
56f8023 data sheet, rev. 3 28 freescale semiconductor preliminary gpioc1 (ana1) 11 input/ output analog input input port c gpio ? this gpio pin can be individually programmed as an input or output pin. ana1 ? analog input to adc a, channel 1. after reset, the default state is gpioc1. gpioc2 (ana2) (v refha ) 10 input/ output analog input analog input input port c gpio ? this gpio pin can be individually programmed as an input or output pin. ana2 ? analog input to adc a, channel 2. v refha ? analog reference voltage high (adc a). after reset, the default state is gpioc2. gpioc4 (anb0 & cmpbi3) 5 input/ output analog input input port c gpio ? this gpio pin can be individually programmed as an input or output pin. anb0 ? analog input to adc b, channel 0. comparator b, input 3 ? this is an analog input to comparator b. when used as an analog input, the signal goes to both the anb0 and cmpbi3. after reset, the default state is gpioc4. gpioc5 (anb1) 6 input/ output analog input input port c gpio ? this gpio pin can be individually programmed as an input or output pin. anb1 ? analog input to adc b, channel 1. after reset, the default state is gpioc5. gpioc6 (anb2) (v refhb ) 7 input/ output analog input input input port c gpio ? this gpio pin can be individually programmed as an input or output pin. anb2 ? analog input to adc b, channel 2. v refhb ? analog reference voltage high (adc b). after reset, the default state is gpioc6. return to table 2-2 table 2-3 56f8023 signal and package information for th e 32-pin lqfp (continued) signal name lqfp pin no. type state during reset signal description
56f8023 signal pins 56f8023 data sheet, rev. 3 freescale semiconductor 29 preliminary tdi (gpiod0) 30 input input/ output input, internal pull-up enabled test data input ? this input pin provides a serial input data stream to the jtag/eonce port. it is sampled on the rising edge of tck and has an on-chip pull-up resistor. port d gpio ? this gpio pin can be individually programmed as an input or output pin. after reset, the default state is tdi. tdo (gpiod1) 32 output input/ output output, tri-stated, internal pull-up enabled test data output ? this tri-stateable output pin provides a serial output data stream from the jtag/eonce port. it is driven in the shift-ir and shift-dr controller states, and changes on the falling edge of tck. port d gpio ? this gpio pin can be individually programmed as an input or output pin. after reset, the default state is tdo. tck (gpiod2) 14 input input/ output input, internal pull-up enabled test clock input ? this input pin provides a gated clock to synchronize the test logic and shift serial data to the jtag/eonce port. the pin is connected internally to a pull-up resistor. a schmitt trigger input is used for noise immunity. port d gpio ? this gpio pin can be individually programmed as an input or output pin. after reset, the default state is tck. tms (gpiod3) 31 input input/ output input, internal pull-up enabled test mode select input ? this input pin is used to sequence the jtag tap controller?s state machine. it is sampled on the rising edge of tck and has an on-chip pull-up resistor. port d gpio ? this gpio pin can be individually programmed as an input or output pin. after reset, the default state is tms. note: always tie the tms pin to v dd through a 2.2k resistor. return to table 2-2 table 2-3 56f8023 signal and package information for th e 32-pin lqfp (continued) signal name lqfp pin no. type state during reset signal description
56f8023 data sheet, rev. 3 30 freescale semiconductor preliminary part 3 occs 3.1 overview the on-chip clock synthesis (occs) module allows designers using an internal relaxation oscillator, an external crystal, or an external clock to run 56f8000 fami ly devices at user-sel ectable frequencies up to 32mhz. for details, see the occs chapter in the 56f802x and 56f803x peri pheral reference manual . 3.2 features the occs module interfaces to the oscillat or and pll and offers these features: ? internal relaxation oscillator ? ability to power down the internal rela xation oscillator or crystal oscillator ? ability to put the internal rela xation oscillator into standby mode ? 3-bit postscaler provides control for the pll output ? ability to power down the pll ? provides a 2x system clock which operates at twice the system clock to the system integration module (sim) ? provides a 3x system clock which operates at thr ee times the system clock to pwm and timer modules ? safety shutdown feature is availabl e if the pll reference clock is lost ? can be driven from an external clock source the clock generation module provid es the programming interface for the pll, internal relaxation oscillator, and cr ystal oscillator. 3.3 operating modes in 56f8000 family devices, an internal oscillator, an external crystal, or an external clock source can be used to provide a reference clock to the sim. the 2x system clock source output from the occs ca n be described by one of the following equations: 2x system frequency = oscillator frequency 2x system frequency = (oscillato r frequency x 8) / (postscaler) where: postscaler = 1, 2, 4, 8, 16, or 32 the sim is responsible for further dividing these frequencies by two, wh ich will insure a 50% duty cycle in the system clock output.
internal clock source 56f8023 data sheet, rev. 3 freescale semiconductor 31 preliminary the 56f8000 family devices? on-chip clock s ynthesis module has the following registers: ? control register (occs_ctrl) ? divide-by register (occs_divby) ? status register (occs_stat) ? shutdown register (occs_shutdn) ? oscillator control register (occs_octrl) for more information on these registers, please refer to the 56f802x and 56f803x p eripheral reference manual. 3.4 internal clock source an internal relaxation osci llator can supply the refere nce frequency when an exte rnal frequency source or crystal is not used. it is optimiz ed for accuracy and pr ogrammability while provi ding several power-saving configurations which accommodate different operating conditions. the in ternal relaxation oscillator has very little temperature and voltage variability. to optimize power, the architectu re supports a standby state and a power-down state. during a boot or reset sequence, the relaxation oscill ator is enabled by defaul t (the precs bit in the pllcr word is set to 0). application code can then also switch to the extern al clock sour ce and power down the internal oscillator, if de sired. if a changeover be tween internal and exte rnal clock sources is required at power-on, the user must en sure that the clock source is not switched until the desired external clock source is en abled and stable. to compensate for variances in th e device manufacturing process, the ac curacy of the relaxation oscillator can be incrementally adjusted to within + 0.078% of 8mhz by trim ming an internal capacitor. bits 0-9 of the osctl (oscillator control) register allow the user to set in an additional offset (tri m) to this preset value to increase or decrease cap acitance. each unit adde d or subtracted change s the output frequency by about 0.078% of 8mhz, allowing increm ental adjustment until the desire d frequency accuracy is achieved. the center frequency of the internal os cillator is calibrated at the factory to 8mhz and the trim value is stored in the flash information block and loaded to the fmopt1 register at reset. when using the relaxation oscillator, the boot code should read the fmopt1 register and set this value as osctl trim. for further information, see the 56f802x and 56f803x peripheral reference manual . 3.5 crystal oscillator the internal crystal oscillat or circuit is designed to in terface with a parallel-resonant crystal resonator in a frequency range of 4-8mhz, specif ied for the external crystal. figure 3-1 shows a typical crystal oscillator circuit. follow the crystal supplier ? s recommendations when selecting a crystal, since crystal parameters determine the component values required to provid e maximum stability and re liable start-up. the load capacitance values used in the oscillator circuit de sign should include all stra y layout capacitances. the crystal and associated components should be mounted as near as pos sible to the extal and xtal pins to minimize output distortion an d start-up stabilization time.
56f8023 data sheet, rev. 3 32 freescale semiconductor preliminary figure 3-1 external cryst al oscillator circuit 3.6 ceramic resonator the internal crystal oscillator circui t is also designed to interface with a ceramic resonator in the frequency range of 4-8mhz. figure 3-2 shows the typical 2- and 3-terminal ceramic resonators and their circuits. follow the resonator supplier ? s recommendations when selecting a resonator, since their parameters determine the component values required to provide maximum stability and re liable start up. the load capacitance values used in the re sonator circuit design should includ e all stray layout capacitances. the resonator and associated components should be mounte d as near as possible to the extal and xtal pins to minimize output distortion an d start-up stabilization time. figure 3-2 external cera mic resonator circuit 3.7 external clock input - crystal oscillator option the recommended method of connecting an external cl ock is illustrated in figure 3-3 . the external clock source is connected to xtal and th e extal pin is grounded. the external clock input must be generated using a relatively low impedance driver. sample external crystal parameters: r z = 750 k note: if the operating temperature range is limited to below 85 o c (105 o c junction), then r z = 10 meg extal xtal r z cl1 cl2 crystal frequency = 4 - 8mhz (optimized for 8mhz) extal xtal r z extal xtal r z sample external cerami c resonator parameters: r z = 750 k extal xtal r z c1 cl1 cl2 c2 resonator frequency = 4 - 8mhz (optimized for 8mhz) 3 terminal 2 terminal
alternate external clock input 56f8023 data sheet, rev. 3 freescale semiconductor 33 preliminary figure 3-3 connecting an extern al clock signal using xtal 3.8 alternate external clock input the recommended method of connecting an external clock is illustrated in figure 3-3 . the external clock source is connected to gpio6/ rxd (primary) or gpiob5/ta1 /fault3/xtal/extal (secondary). the user has the option of us ing gpio6/rxd/clkin or gpiob5 /ta1/fault3/clkin as external clock input. figure 3-4 connecting an extern al clock signal using gpio part 4 memory maps 4.1 introduction the 56f8023 device is a 16-bit motor-control chip ba sed on the 56800e core. it uses a harvard-style architecture with two i ndependent memory spaces for data and program. on-chip ram is shared by both spaces and flash memory is used only in program space. this section provides memory maps for: ? program address space, including the interrupt vector table ? data address space, including the eonce memory and peripheral memory maps on-chip memory sizes for the device are summarized in table 4-1 . flash memories? restrictions are identified in the ?use restrictions? column of table 4-1 . table 4-1 chip memo ry configurations on-chip memory 56f8023 use restrictions program flash (pflash) 16k x 16 or 32kb erase / program via flash interface unit and word writes to cdbw 56f8023 external clock xtal extal gnd or gpio clkmode = 1 56f8023 gpio external clock
56f8023 data sheet, rev. 3 34 freescale semiconductor preliminary 4.2 interrupt vector table table 4-2 provides the 56f8023?s reset and inte rrupt priority structure, in cluding on-chip peripherals. the table is organized with hi gher-priority vectors at the top and lowe r-priority interrupts lower in the table. as indicated, the priority of an in terrupt can be assigned to different levels, allo wing some control over interrupt priorities. all le vel 3 interrupts will be serviced before level 2, and so on. for a selected priority level, the lowest vector num ber has the highest priority. the location of the vector table is determined by the vector base addr ess (vba). please see section 5.6.8 for the reset value of the vba. by default, vba = 0, and the reset address and cop reset address will correspond to vector 0 and 1 of the interrupt vector table. in these instances, the first tw o locations in the vector ta ble must contain branch or jmp instructions. all other entries must contain jsr instructions. unified ram (ram) 2k x 16 or 4kb usable by both the program and data memory spaces table 4-2 interrupt v ector table contents 1 peripheral vector number priority level vector base address + interrupt function core p:$00 reserved for reset overlay 2 core p:$02 reserved for cop reset overlay core 2 3 p:$04 illegal instruction core 3 3 p:$06 sw interrupt 3 core 4 3 p:$08 hw stack overflow core 5 3 p:$0a misaligned long word access core 6 1-3 p:$0c eonce step counter core 7 1-3 p:$0e eonce breakpoint unit core 8 1-3 p:$10 eonce trace buffer core 9 1-3 p:$12 eonce transmit register empty core 10 1-3 p:$14 eonce receive register full core 11 2 p:$16 sw interrupt 2 core 12 1 p:$18 sw interrupt 1 core 13 0 p:$1a sw interrupt 0 14 reserved lvi 15 1-3 p:$1e low-voltage detector (power sense) pll 16 1-3 p:$20 phase-locked loop fm 17 0-2 p:$22 fm access error interrupt table 4-1 chip memo ry configurations on-chip memory 56f8023 use restrictions
interrupt vector table 56f8023 data sheet, rev. 3 freescale semiconductor 35 preliminary fm 18 0-2 p:$24 fm command complete fm 19 0-2 p:$26 fm command, data , and address buffers empty 20 - 23 reserved gpiod 24 0-2 p:$30 gpiod gpioc 25 0-2 p:$32 gpioc gpiob 26 0-2 p:$34 gpiob gpioa 27 0-2 p:$36 gpioa qspi0 28 0-2 p:$38 qspi 0 receiver full qspi0 29 0-2 p:$3a qspi0 transmitter empty 30 - 31 reserved qsci0 32 0-2 p:$40 qsci0 transmitter empty qsci0 33 0-2 p:$42 qsci0 transmitter idle qsci0 34 0-2 p:$44 qsci0 receiver error qsci0 35 0-2 p:$46 qsci0 receiver full 36 - 39 reserved i2c 40 0-2 p:$50 i 2 c error i2c 41 0-2 p:$52 i 2 c general i2c 42 0-2 p:$54 i 2 c receive i2c 43 0-2 p:$56 i 2 c transmit i2c 44 0-2 p:$58 i 2 c status tmra 45 0-2 p:$5a timer a, channel 0 tmra 46 0-2 p:$5c timer a, channel 1 tmra 47 0-2 p:$5e timer a, channel 2 tmra 48 0-2 p:$60 timer a, channel 3 49 - 52 reserved cmpa 53 0-2 p:$6a comparator a cmpb 54 0-2 p:$6c comparator b pit0 55 0-2 p:$6e interval timer 0 56 - 57 reserved adc 58 0-2 p:$74 adc a conversion complete adc 59 0-2 p:$76 adc b conversion complete adc 60 0-2 p:$78 adc zero crossing or limit error pwm 61 0-2 p:$7a reload pwm pwm 62 0-2 p:$7c pwm fault swilp 63 -1 p:$7e sw interrupt low priority 1. two words are allocated for each entry in the vector table. this does not allow the full address range to be referenced from the vector table, providing only 19 bits of address. 2. if the vba is set to $0000, the first two locations of the vector table will overlay the chip reset addresses since the reset address would match the base of this vector table. table 4-2 interrupt vector table contents 1 (continued) peripheral vector number priority level vector base address + interrupt function
56f8023 data sheet, rev. 3 36 freescale semiconductor preliminary 4.3 program map the program memory map is shown in table 4-3 . 4.4 data map table 4-3 program memory map 1 at reset 1. all addresses are 16-bit word addresses. begin/end address memory allocation p: $1f ffff p: $00 8800 reserved p: $00 87ff p: $00 8000 on-chip ram 2 4kb 2. this ram is shared with data space starting at address x: $00 0000; see figure 4-1 . p: $00 7fff p: $00 4000 internal program flash 32kb cop reset address = $00 4002 boot location = $00 4000 p: $00 3fff p: $00 0000 reserved table 4-4 data memory map 1 1. all addresses are 16-bit word addresses. begin/end address memory allocation x:$ff ffff x:$ff ff00 eonce 256 locations allocated x:$ff feff x:$01 0000 reserved x:$00 ffff x:$00 f000 on-chip peripherals 4096 locations allocated x:$00 efff x:$00 8800 reserved x:$00 87ff x:$00 8000 reserved x:$00 7fff x:$00 0800 reserved x:$00 07ff x:$00 0000 on-chip data ram 4kb 2 2. this ram is shared with program space starting at p: $00 8000; see figure 4-1 .
eonce memory map 56f8023 data sheet, rev. 3 freescale semiconductor 37 preliminary figure 4-1 dual port ram 4.5 eonce memory map figure 4-5 lists all eonce registers necessary to access or control the eonce. table 4-5 eonce memory map address register acronym register name x:$ff ffff otx1 / orx1 transmit register upper word receive register upper word x:$ff fffe otx / orx (32 bits) transmit register receive register x:$ff fffd otxrxsr transmit and receive status and control register x:$ff fffc oclsr core lock / unlock status register x:$ff fffb - x:$ff ffa1 reserved x:$ff ffa0 ocr control register x:$ff ff9f instruction step counter x:$ff ff9e oscntr (24 bits) instruction step counter x:$ff ff9d osr status register x:$ff ff9c obase peripheral base address register x:$ff ff9b otbcr trace buffer control register x:$ff ff9a otbpr trace bu ffer pointer register x:$ff ff99 trace buffer register stages x:$ff ff98 otb (21 - 24 bits/stage) trace buffer register stages x:$ff ff97 breakpoint unit control register x:$ff ff96 obcr (24 bits) breakpoint unit control register x:$ff ff95 breakpoint unit address register 1 x:$ff ff94 obar1 (24 bits) breakpoint unit address register 1 reserved ram reserved flash reserved eonce peripherals reserved ram dual port ram program data
56f8023 data sheet, rev. 3 38 freescale semiconductor preliminary 4.6 peripheral memory-mapped registers on-chip peripheral registers are pa rt of the data memory map on th e 56800e series. these locations may be accessed with the same addressing modes used for ordinary data memory, except all peripheral registers should be read or wr itten using word accesses only. table 4-6 summarizes base addresses for the set of pe ripherals on the 56f8023 de vice. peripherals are listed in order of the base address. the following tables list all of the peripheral registers requi red to control or access the peripherals. x:$ff ff93 breakpoint unit address register 2 x:$ff ff92 obar2 (32 bits) breakpoint unit address register 2 x:$ff ff91 breakpoint unit mask register 2 x:$ff ff90 obmsk (32 bits) breakpoint unit mask register 2 x:$ff ff8f reserved x:$ff ff8e obcntr eonce breakpoint unit counter x:$ff ff8d reserved x:$ff ff8c reserved x:$ff ff8b reserved x:$ff ff8a oescr external signal control register x:$ff ff89 - x:$ff ff00 reserved table 4-6 data memory periph eral base address map summary peripheral prefix base address table number timer a tmra x:$00 f000 4-7 adc adc x:$00 f080 4-8 pwm pwm x:$00 f0c0 4-9 itcn itcn x:$00 f0e0 4-10 sim sim x:$00 f100 4-11 cop cop x:$00 f120 4-12 clk, pll, osc occs x:$00 f130 4-13 power supervisor ps x:$00 f140 4-14 gpio port a gpioa x:$00 f150 4-15 gpio port b gpiob x:$00 f160 4-16 gpio port c gpioc x:$00 f170 4-17 gpio port d gpiod x:$00 f180 4-18 pit 0 pit0 x:$00 f190 4-19 table 4-5 eonce memo ry map (continued) address register acronym register name
peripheral memory-mapped registers 56f8023 data sheet, rev. 3 freescale semiconductor 39 preliminary dac 0 dac0 x:$00 f1c0 4-20 dac 1 dac1 x:$00 f1d0 4-21 comparator a cmpa x:$00 f1e0 4-22 comparator b cmpb x:$00 f1f0 4-23 qsci 0 sci0 x:$00 f200 4-24 qspi 0 spi0 x:$00 f220 4-25 i 2 c i2c x:$00 f280 4-26 fm fm x:$00 f400 4-27 table 4-7 quad timer a registers address map (tmra_base = $00 f000) register acronym address offset register description tmra0_comp1 $0 compare register 1 tmra0_comp2 $1 compare register 2 tmra0_capt $2 capture register tmra0_load $3 load register tmra0_hold $4 hold register tmra0_cntr $5 counter register tmra0_ctrl $6 control register tmra0_sctrl $7 status and control register tmra0_cmpld1 $8 comparator load register 1 tmra0_cmpld2 $9 comparator load register 2 tmra0_csctrl $a comparator status and control register tmra0_filt $b input filter register reserved tmra0_enbl $f timer channel enable register tmra1_comp1 $10 compare register 1 tmra1_comp2 $11 compare register 2 tmra1_capt $12 capture register tmra1_load $13 load register tmra1_hold $14 hold register tmra1_cntr $15 counter register tmra1_ctrl $16 control register tmra1_sctrl $17 status and control register tmra1_cmpld1 $18 comparator load register 1 tmra1_cmpld2 $19 comparator load register 2 tmra1_csctrl $1a comparator status and control register table 4-6 data memory peripheral base address map su mmary (continued) peripheral prefix base address table number
56f8023 data sheet, rev. 3 40 freescale semiconductor preliminary tmra1_filt $1b input filter register reserved tmra2_comp1 $20 compare register 1 tmra2_comp2 $21 compare register 2 tmra2_capt $22 capture register tmra2_load $23 load register tmra2_hold $24 hold register tmra2_cntr $25 counter register tmra2_ctrl $26 control register tmra2_sctrl $27 status and control register tmra2_cmpld1 $28 comparator load register 1 tmra2_cmpld2 $29 comparator load register 2 tmra2_csctrl $2a comparator status and control register tmra2_filt $2b input filter register reserved tmra3_comp1 $30 compare register 1 tmra3_comp2 $31 compare register 2 tmra3_capt $32 capture register tmra3_load $33 load register tmra3_hold $34 hold register tmra3_cntr $35 counter register tmra3_ctrl $36 control register tmra3_sctrl $37 status and control register tmra3_cmpld1 $38 comparator load register 1 tmra3_cmpld2 $39 comparator load register 2 tmra3_csctrl $3a comparator status and control register tmra3_filt $3b input filter register reserved table 4-8 analog-to-digital c onverter registers address map (adc_base = $00 f080) register acronym address offset register description adc_ctrl1 $0 control register 1 adc_ctrl2 $1 control register 2 adc_zxctrl $2 zero crossing control register adc_clist 1 $3 channel list register 1 table 4-7 quad timer a regi sters address map (continued) (tmra_base = $00 f000) register acronym address offset register description
peripheral memory-mapped registers 56f8023 data sheet, rev. 3 freescale semiconductor 41 preliminary adc_clist 2 $4 channel list register 2 adc_clist 3 $5 channel list register 3 adc_clist 4 $6 channel list register 4 adc_sdis $7 sample disable register adc_stat $8 status register adc_rdy $9 conversion ready register adc_limstat $a limit status register adc_zxstat $b zero crossing status register adc_rslt0 $c result register 0 adc_rslt1 $d result register 1 adc_rslt2 $e result register 2 adc_rslt3 $f result register 3 adc_rslt4 $10 result register 4 adc_rslt5 $11 result register 5 adc_rslt6 $12 result register 6 adc_rslt7 $13 result register 7 adc_rslt8 $14 result register 8 adc_rslt9 $15 result register 9 adc_rslt10 $16 result register 10 adc_rslt11 $17 result register 11 adc_rslt12 $18 result register 12 adc_rslt13 $19 result register 13 adc_rslt14 $1a result register 14 adc_rslt15 $1b result register 15 adc_lolim0 $1c low limit register 0 adc_lolim1 $1d low limit register 1 adc_lolim2 $1e low limit register 2 adc_lolim3 $1f low limit register 3 adc_lolim4 $20 low limit register 4 adc_lolim5 $21 low limit register 5 adc_lolim6 $22 low limit register 6 adc_lolim7 $23 low limit register 7 adc_hilim0 $24 high limit register 0 adc_hilim1 $25 high limit register 1 adc_hilim2 $26 high limit register 2 adc_hilim3 $27 high limit register 3 table 4-8 analog-to-digital converte r registers address map (continued) (adc_base = $00 f080) register acronym address offset register description
56f8023 data sheet, rev. 3 42 freescale semiconductor preliminary adc_hilim4 $28 high limit register 4 adc_hilim5 $29 high limit register 5 adc_hilim6 $2a high limit register 6 adc_hilim7 $2b high limit register 7 adc_offst0 $2c offset register 0 adc_offst1 $2d offset register 1 adc_offst2 $2e offset register 2 adc_offst3 $2f offset register 3 adc_offst4 $30 offset register 4 adc_offst5 $31 offset register 5 adc_offst6 $32 offset register 6 adc_offst7 $33 offset register 7 adc_pwr $34 power control register adc_cal $35 calibration register reserved table 4-9 pulse width modul ator registers address map (pwm_base = $00 f0c0) register acronym address offset register description pwm_ctrl $0 control register pwm_fctrl $1 fault control register pwm_fltack $2 fault status acknowledge register pwm_out $3 output control register pwm_cntr $4 counter register pwm_cmod $5 counter modulo register pwm_val0 $6 value register 0 pwm_val1 $7 value register 1 pwm_val2 $8 value register 2 pwm_val3 $9 value register 3 pwm_val4 $a value register 4 pwm_val5 $b value register 5 pwm_dtim0 $c dead time register 0 pwm_dtim1 $d dead time register 1 pwm_dmap1 $e disable mapping register 1 pwm_dmap2 $f disable mapping register 2 pwm_cnfg $10 configure register table 4-8 analog-to-digital converte r registers address map (continued) (adc_base = $00 f080) register acronym address offset register description
peripheral memory-mapped registers 56f8023 data sheet, rev. 3 freescale semiconductor 43 preliminary pwm_cctrl $11 channel control register pwm_port $12 port register pwm_icctrl $13 internal correction control register pwm_sctrl $14 source control register pwm_sync $15 synchronization window register pwm_ffilt0 $16 fault0 filter register pwm_ffilt1 $17 fault1 filter register pwm_ffilt2 $18 fault2 filter register pwm_ffilt3 $19 fault3 filter register table 4-10 interrupt contro l registers address map (itcn_base = $00 f0e0) register acronym address offset register description itcn_ipr0 $0 interrupt priority register 0 itcn_ipr1 $1 interrupt priority register 1 itcn_ipr2 $2 interrupt priority register 2 itcn_ipr3 $3 interrupt priority register 3 itcn_ipr4 $4 interrupt priority register 4 itcn_ipr5 $5 interrupt priority register 5 itcn_ipr6 $6 interrupt priority register 6 itcn_vba $7 vector base address register itcn_fim0 $8 fast interrupt match 0 register itcn_fival0 $9 fast interrupt ve ctor address low 0 register itcn_fivah0 $a fast interrupt vector address high 0 register itcn_fim1 $b fast interrupt match 1 register itcn_fival1 $c fast interrupt ve ctor address low 1 register itcn_fivah1 $d fast interrupt vector address high 1 register itcn_irqp0 $e irq pending register 0 itcn_irqp1 $f irq pending register 1 itcn_irqp2 $10 irq pending register 2 itcn_irqp3 $11 irq pending register 3 reserved itcn_ictrl $16 interrupt control register reserved table 4-9 pulse width modulator registers address map (continued) (pwm_base = $00 f0c0) register acronym address offset register description
56f8023 data sheet, rev. 3 44 freescale semiconductor preliminary table 4-11 sim registers address map (sim_base = $00 f100) register acronym address offset register description sim_ctrl $0 control register sim_rstat $1 reset status register sim_swc0 $2 software control register 0 sim_swc1 $3 software control register 1 sim_swc2 $4 software control register 2 sim_swc3 $5 software control register 3 sim_mshid $6 most significant half jtag id sim_lshid $7 least signifi cant half jtag id sim_pwr $8 power control register reserved sim_clkout $a clock out select register sim_pcr $b peripheral clock rate register sim_pce0 $c peripheral clock enable register 0 sim_pce1 $d peripheral clock enable register 1 sim_sd0 $e peripheral stop disable register 0 sim_sd1 $f peripheral stop disable register 1 sim_iosahi $10 i/o short address location high register sim_iosalo $11 i/o short address location low register sim_prot $12 protection register sim_gpsa0 $13 gpio peripheral se lect register 0 for gpioa reserved sim_gpsb0 $15 gpio peripheral se lect register 0 for gpiob sim_gpsb1 $16 gpio peripheral se lect register 1 for gpiob reserved sim_iss0 $18 internal source select register 0 for pwm sim_iss1 $19 internal source select register 1 for dacs sim_iss2 $1a internal source select register 2 for tmra reserved table 4-12 computer operating properly registers address map (cop_base = $00 f120) register acronym address offset register description cop_ctrl $0 control register cop_tout $1 time-out register
peripheral memory-mapped registers 56f8023 data sheet, rev. 3 freescale semiconductor 45 preliminary cop_cntr $2 counter register table 4-13 clock generation module registers address map (occs_base = $00 f130) register acronym address offset register description occs_ctrl $0 control register occs_divby $1 divide-by register occs_stat $2 status register reserved occs_octrl $5 oscillator control register occs_clkchk $6 clock check register occs_prot $7 protection register table 4-14 power supervisor registers address map (ps_base = $00 f140) register acronym address offset register description ps_ctrl $0 control register ps_stat $1 status register reserved table 4-15 gpioa re gisters address map (gpioa_base = $00 f150) register acronym address offset register description gpioa_pupen $0 pull-up enable register gpioa_data $1 data register gpioa_ddir $2 data direction register gpioa_peren $3 peripheral enable register gpioa_iassrt $4 interrupt assert register gpioa_ien $5 interrupt enable register gpioa_iepol $6 interrupt edge polarity register gpioa_ipend $7 interrupt pending register gpioa_iedge $8 interrupt edge-sensitive register gpioa_ppoutm $9 push-pull output mode control register gpioa_rdata $a raw data input register gpioa_drive $b output drive strength control register table 4-12 computer operating properly registers address map (cop_base = $00 f120) register acronym address offset register description
56f8023 data sheet, rev. 3 46 freescale semiconductor preliminary table 4-16 gpiob re gisters address map (gpiob_base = $00 f160) register acronym address offset register description gpiob_pupen $0 pull-up enable register gpiob_data $1 data register gpiob_ddir $2 data direction register gpiob_peren $3 peripheral enable register gpiob_iassrt $4 interru pt assert register gpiob_ien $5 interrupt enable register gpiob_iepol $6 interrupt edge polarity register gpiob_ipend $7 interrupt pending register gpiob_iedge $8 interrupt edge-sensitive register gpiob_ppoutm $9 push-pull output mode control register gpiob_rdata $a raw data input register gpiob_drive $b output drive strength control register table 4-17 gpioc re gisters address map (gpioc_base = $00 f170) register acronym address offset register description gpioc_pupen $0 pull-up enable register gpioc_data $1 data register gpioc_ddir $2 data direction register gpioc_peren $3 peripheral enable register gpioc_iassrt $4 interrupt assert register gpioc_ien $5 interrupt enable register gpioc_iepol $6 interrupt edge polarity register gpioc_ipend $7 interrupt pending register gpioc_iedge $8 interrupt edge-sensitive register gpioc_ppoutm $9 push-pull output mode control register gpioc_rdata $a raw data input register gpioc_drive $b output drive strength control register
peripheral memory-mapped registers 56f8023 data sheet, rev. 3 freescale semiconductor 47 preliminary table 4-18 gpiod re gisters address map (gpiod_base = $00 f180) register acronym address offset register description gpiod_pupen $0 pull-up enable register gpiod_data $1 data register gpiod_ddir $2 data direction register gpiod_peren $3 peripheral enable register gpiod_iassrt $4 interr upt assert register gpiod_ien $5 interrupt enable register gpiod_iepol $6 interrupt edge polarity register gpiod_ipend $7 interrupt pending register gpiod_iedge $8 interrupt edge-sensitive register gpiod_ppoutm $9 push-pull output mode control register gpiod_rdata $a raw data input register gpiod_drive $b output drive strength control register table 4-19 programmable interval timer 0 registers address map (pit0_base = $00 f190) register acronym address o ffset register description pit0_ctrl $0 control register pit0_mod $1 modulo register pit0_cntr $2 counter register table 4-20 digital-to-analog c onverter 0 registers address map (dac0_base = $00 f1c0) register acronym address o ffset register description dac0_ctrl $0 control register dac0_data $1 data register dac0_step $2 step register dac0_minval $3 minimum value register dac0_maxval $4 maximum value register
56f8023 data sheet, rev. 3 48 freescale semiconductor preliminary table 4-21 digital-to-analog c onverter 0 registers address map (dac0_base = $00 f1c0) register acronym address o ffset register description dac0_ctrl $0 control register dac0_data $1 data register dac0_step $2 step register dac0_minval $3 minimum value register dac0_maxval $4 maximum value register table 4-22 comparator a registers address map (cmpa_base = $00 f1e0) register acronym address o ffset register description cmpa_ctrl $0 control register cmpa_stat $1 status register cmpa_filt $2 filter register table 4-23 comparator b registers address map (cmpb_base = $00 f1f0) register acronym address o ffset register description cmpb_ctrl $0 control register cmpb_stat $1 status register cmpb_filt $2 filter register table 4-24 queued serial communicati on interface 0 registers address map (qsci0_base = $00 f200) register acronym address o ffset register description qsci0_rate $0 baud rate register qsci0_ctrl1 $1 control register 1 qsci0_ctrl2 $2 control register 2 qsci0_stat $3 status register qsci0_data $4 data register
peripheral memory-mapped registers 56f8023 data sheet, rev. 3 freescale semiconductor 49 preliminary table 4-25 queued serial periphera l interface 0 regi sters address map (qspi0_base = $00 f220) register acronym address offset register description qspi0_sctrl $0 status and control register qspi0_dsctrl $1 data size and control register qspi0_drcv $2 data receive register qspi0_dxmit $3 data transmit register qspi0_fifo $4 fifo control register qspi0_delay $5 delay register table 4-26 i 2 c registers address map (i2c_base = $00 f280) register acronym address offset register description i2c_ctrl $0 control register i2c_tar $2 target address register i2c_sar $4 slave address register i2c_data $8 rx/tx data buffer and command register i2c_sshcnt $a standard speed clock scl high count register i2c_sslcnt $c standard speed clock scl low count register i2c_fshcnt $e fast speed clock scl high count register i2c_fslcnt $10 fast speed clock scl low count register i2c_istat $16 interrupt status register i2c_imask $18 interrupt mask register i2c_ristat $1a raw interrupt status register i2c_rxft $1c receive fifo threshold register i2c_txft $1e transmit fifo threshold register i2c_clrint $20 clear combined and individual interrupts register i2c_clrrxund $22 clear rx_under interrupt register i2c_clrrxovr $24 clear rx_over interrupt register i2c_clrtxovr $26 clear tx_over interrupt register i2c_clrrdreq $28 clear rd_req interrupt register i2c_clrtxabrt $2a clear tx_ abrt interrupt register i2c_clrrxdone $2c clear rx _done interrupt register i2c_clract $2e clear acti vity interrupt register i2c_clrstpdet $30 clear stop_det interrupt register i2c_clrstdet $32 clear start_det interrupt register i2c_clrgc $34 clear gen_call interrupt register
56f8023 data sheet, rev. 3 50 freescale semiconductor preliminary i2c_enbl $36 enable register i2c_stat $38 status register i2c_txflr $3a transmit fifo level register i2c_rxflr $3c receive fifo level register i2c_txabrtsrc $40 transmit abort status register table 4-26 i 2 c registers address map (continued) (i2c_base = $00 f280) register acronym address offset register description
introduction 56f8023 data sheet, rev. 3 freescale semiconductor 51 preliminary part 5 interrupt controller (itcn) 5.1 introduction the interrupt controller (itcn) module arbitrates between various interrupt requests (irqs), signals to the 56800e core when an interrupt of sufficient priori ty exists, and to what a ddress to jump in order to service this interrupt. 5.2 features the itcn module design includes these distinctive features: ? programmable priority levels for each irq ? two programmable fast interrupts ? notification to sim module to restar t clocks out of wait and stop modes ? ability to drive initial address on the address bus after reset for further information, see table 4-2 , interrupt vector table contents. table 4-27 flash module registers address map (fm_base = $00 f400) register acronym address o ffset register description fm_clkdiv $0 clock divider register fm_cnfg $1 configuration register $2 reserved fm_sechi $3 security high half register fm_seclo $4 security low half register $5 - $9 reserved fm_prot $10 protection register $11 - $12 reserved fm_ustat $13 user status register fm_cmd $14 command register $15 - $17 reserved fm_data $18 data buffer register $19 - $a reserved fm_ifropt_1 $1b information option register 1 $1c reserved fm_tstsig $1d test array signature register
56f8023 data sheet, rev. 3 52 freescale semiconductor preliminary 5.3 functional description the interrupt controller is a slave on the ipbus. it contains register s that allow each of the 64 interrupt sources to be set to one of four priority levels (excluding certain inte rrupts that are of fi xed priority). next, all of the interrupt requests of a gi ven level are priority encoded to de termine the lowest numerical value of the active interrupt requests for that level. within a given priority le vel, number 0 is th e highest priority and number 63 is the lowest. 5.3.1 normal interrupt handling once the intc has determined that an interrupt is to be serviced and which interrupt has the highest priority, an interrupt vect or address is generated. no rmal interrupt handling con catenates the vector base address (vba) and the vector number to determine the vector address, generating an offset into the vector table for each interrupt. 5.3.2 interrupt nesting interrupt exceptions may be nested to allow an irq of higher priori ty than the current exception to be serviced. the 56800e core controls th e masking of interrupt priority le vels it will acc ept by setting the i0 and i1 bits in its status register. the ipic bits of the ictr l register reflect the state of the pr iority level being presented to the 56800e core. table 5-1 interrupt mask bit definition sr[9] (i1) sr[8] (i0) exceptions permitted exceptions masked 0 0 priorities 0, 1, 2, 3 none 0 1 priorities 1, 2, 3 priority 0 1 0 priorities 2, 3 priorities 0, 1 1 1 priority 3 priorities 0, 1, 2 table 5-2 interrupt priority encoding ipic_value[1:0] current interrupt priority level required nested exception priority 00 no interrupt or swilp priorities 0, 1, 2, 3 01 priority 0 priorities 1, 2, 3 10 priority 1 priorities 2, 3 11 priority 2 or 3 priority 3
functional description 56f8023 data sheet, rev. 3 freescale semiconductor 53 preliminary 5.3.3 fast interrupt handling fast interrupts are described in the dsp56800e reference manual . the interrupt c ontroller recognizes fast interrupts before the core does. a fast interrupt is de fined (to the itcn) by: 1. setting the priority of the interrupt as level 2, with the appropriate field in the ipr registers 2. setting the fim n register to the appropriate vector number 3. setting the fival n and fivah n registers with the address of the code for the fast interrupt when an interrupt occurs, its vector number is compar ed with the fim0 and fim1 register values. if a match occurs, and it is a level 2 inte rrupt, the itcn handles it as a fast interrupt. the itcn takes the vector address from the appropriate fival n and fivah n registers, instead of gene rating an addres s that is an offset from the vba. the core then fetches the instruction from the indicated vector address and if it is not a jsr, the core starts its fast interrupt handling.
56f8023 data sheet, rev. 3 54 freescale semiconductor preliminary 5.4 block diagram figure 5-1 interrupt controller block diagram 5.5 operating modes the itcn module design contains two major modes of operation: ? functional mode the itcn is in this mode by default. ? wait and stop modes during wait and stop modes, the syst em clocks and the 56800e core are turned off. the itcn will signal a pending irq to the system integr ation module (sim) to restart the clocks and service the irq. an irq can only wake up the core if the irq is enab led prior to entering the wait or stop mode. 5.6 register descriptions a register address is the sum of a base address and an addr ess offset. the base addr ess is defined at the system level and the a ddress offset is define d at the module level. priority level 2 -> 4 decode int1 priority level 2 -> 4 decode int64 level 0 64 -> 6 priority encoder any0 level 3 64 -> 6 priority encoder any3 int vab ipic control 6 6 pic_en iack sr[9:8]
register descriptions 56f8023 data sheet, rev. 3 freescale semiconductor 55 preliminary table 5-3 itcn register summary (itcn_base = $00 f060) register acronym base address + register name section location ipr0 $0 interrupt priority register 0 5.6.1 ipr1 $1 interrupt priority register 1 5.6.2 ipr2 $2 interrupt priority register 2 5.6.3 ipr3 $3 interrupt priority register 3 5.6.4 ipr4 $4 interrupt priority register 4 5.6.5 ipr5 $5 interrupt priority register 5 5.6.6 ipr6 $6 interrupt priority register 6 5.6.7 vba $7 vector base address register 5.6.8 fim0 $8 fast interrupt match 0 register 5.6.9 fival0 $9 fast interrupt 0 vector address low register 5.6.10 fivah0 $a fast interrupt 0 vector address high 0 register 5.6.11 fim1 $b fast interrupt match 1 register 5.6.12 fival1 $c fast interrupt 1 vector address low register 5.6.13 fivah1 $d fast interrupt 1 vector address high register 5.6.14 irqp0 $e irq pending register 0 5.6.15 irqp1 $f irq pending register 1 5.6.16 irqp2 $10 irq pending register 2 5.6.17 irqp3 $11 irq pending register 3 5.6.18 reserved ictrl $16 interrupt control register 5.6.19 reserved
56f8023 data sheet, rev. 3 56 freescale semiconductor preliminary figure 5-2 itcn register map summary add. offset register name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 $0 ipr0 r pll ipl lvi ipl 0 0 rx_reg ipl tx_reg ipl trbuf ipl bkpt_u ipl stpcnt ipl w $1 ipr1 r gpiod ipl 0 0 0 0 0 0 0 0 fm_cbe ipl fm_cc ipl fm_err ipl w $2 ipr2 r qsci0_xmit ipl 0 0 0 0 qspi0_xmit ipl qspi0_rcv ipl gpioa ipl gpiob ipl gpioc ipl w $3 ipr3 r i2c_err ipl 0 0 0 0 0 0 0 0 qsci0_rcv ipl qsci0_rerr ipl qsci0_tidl ipl w $4 ipr4 r tmra_3 ipl tmra_2 ipl tmra_1 ipl tmra_0 ipl i2c_stat ipl i2c_tx ipl i2c_rx ipl i2c_gen ipl w $5 ipr5 r 0 0 pit0 ipl compb ipl compa ipl 0 0 0 0 0 0 0 0 w $6 ipr6 0 0 0 0 pwm_f ipl pwm_rl ipl adc_zc ipl adcb_cc ipl adca_cc ipl 0 0 $7 vba r 0 0 vector_base_address w $8 fim0 r 0 0 0 0 0 0 0 0 0 0 fast interrupt 0 w $9 fival0 r fast interrupt 0 vector address low w $a fivah0 r 0 0 0 0 0 0 0 0 0 0 0 fast interrupt 0 vector address high w $b fim1 r 0 0 0 0 0 0 0 0 0 0 fast interrupt 1 w $c fival1 r fast interrupt 1 vector address low w $d fivah1 r 0 0 0 0 0 0 0 0 0 0 0 fast interrupt 1 vector address high w $e irqp0 r pending[16:2] 1 w $f irqp1 r pending[32:17] w $10 irqp2 r pending[48:33] w $11 irqp3 r pending[63:49] w reserved $16 ictrl rint ipic vab int_ dis 1 1 1 0 0 w reserved = reserved
register descriptions 56f8023 data sheet, rev. 3 freescale semiconductor 57 preliminary 5.6.1 interrupt priority register 0 (ipr0) figure 5-3 interrupt prio rity register 0 (ipr0) 5.6.1.1 pll loss of referenc e or change in lock sta tus interrupt priority level (pll ipl)?bits 15?14 this field is used to set the interrupt priority levels for the pll loss of reference or change in lock status irq. this irq is limited to priorities 1 through 3. it is disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 1 ? 10 = irq is priority level 2 ? 11 = irq is priority level 3 5.6.1.2 low voltage detector interru pt priority level (lvi ipl)?bits 13?12 this field is used to set the interrupt priority levels for the low voltage detector irq. this irq is limited to priorities 1 through 3 an d is disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 1 ? 10 = irq is priority level 2 ? 11 = irq is priority level 3 5.6.1.3 reserved?bits 11?10 this bit field is reserved. each bit must be set to 0. 5.6.1.4 eonce receive register full interrupt priority level (rx_reg ipl)? bits 9?8 this field is used to set the interrupt priority level for the eonce receive register full irq. this irq is limited to priorities 1 throu gh 3. it is disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 1 ? 10 = irq is priority level 2 ? 11 = irq is priority level 3 base + $0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read pll ipl lvi ipl 0 0 rx_reg ipl tx_reg ipl trbuf ipl bkpt_u ipl stpcnt ipl write reset 0 0 0 0 0 0 0 000000000
56f8023 data sheet, rev. 3 58 freescale semiconductor preliminary 5.6.1.5 eonce transmit regist er empty interrupt priority level (tx_reg ipl)? bits 7?6 this field is used to set the interr upt priority level for the eonce tran smit register empt y irq. this irq is limited to priorities 1 thr ough 3. it is disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 1 ? 10 = irq is priority level 2 ? 11 = irq is priority level 3 5.6.1.6 eonce trace buffer interrupt priority level (trbuf ipl)? bits 5?4 this field is used to set the interrupt priority level for the eonce trace buffer irq. this irq is limited to priorities 1 through 3. it is disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 1 ? 10 = irq is priority level 2 ? 11 = irq is priority level 3 5.6.1.7 eonce breakpoint un it interrupt priority level (bkpt_u ipl)? bits 3?2 this field is used to set the interr upt priority level for the eonce breakpoi nt unit irq. this irq is limited to priorities 1 through 3. it is disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 1 ? 10 = irq is priority level 2 ? 11 = irq is priority level 3 5.6.1.8 eonce step counte r interrupt priority level (stpcnt ipl)? bits 1?0 this field is used to set the interrupt priority leve l for the eonce step counter irq. this irq is limited to priorities 1 through 3. it is disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 1 ? 10 = irq is priority level 2 ? 11 = irq is priority level 3
register descriptions 56f8023 data sheet, rev. 3 freescale semiconductor 59 preliminary 5.6.2 interrupt priority register 1 (ipr1) figure 5-4 interrupt prio rity register 1 (ipr1) 5.6.2.1 gpiod interrupt priorit y level (gpiod ipl)?bits 15?14 this field is used to set the interrupt priority level for the gpiod irq. this irq is limited to priorities 0 through 2. it is disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.2.2 reserved?bits 13?6 this bit field is reserved. each bit must be set to 0. 5.6.2.3 fm command, data, address buffers empty interrupt priority level (fm_cbe ipl)?bits 5?4 this field is used to set the in terrupt priority level for the fm command, data address buffers empty irq. this irq is limited to priorities 0 through 2. it is disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.2.4 fm command complete inte rrupt priority level (fm_cc ipl)?bits 3?2 this field is used to set the in terrupt priority level for the fm command complete irq. this irq is limited to priorities 0 throu gh 2. it is disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 base + $1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read gpiod ipl 0 0 0 0 0 0 0 0 fm_cbe ipl fm_cc ipl fm_err ipl write reset 0 0 0 0 0 0 0 0 0 0 000000
56f8023 data sheet, rev. 3 60 freescale semiconductor preliminary 5.6.2.5 fm error interrupt prio rity level (fm_e rr ipl)?bits 1?0 this field is used to set the interrupt priority level for the fm error irq. this irq is limited to priorities 0 through 2. it is disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.3 interrupt priority register 2 (ipr2) figure 5-5 interrupt prio rity register 2 (ipr2) 5.6.3.1 qsci 0 transmitter empty inte rrupt priority level (qsci0_xmit ipl)? bits 15?14 this field is used to set the inte rrupt priority level fo r the qsci0 transmitter empty irq. this irq is limited to priorities 0 throu gh 2. it is disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.3.2 reserved?bits 13?10 this bit field is reserved. each bit must be set to 0. 5.6.3.3 qspi 0 transmitter empty i nterrupt priority level (qspi0_xmit ipl)? bits 9?8 this field is used to set the interrupt priority le vel for the qspi0 transmitte r empty irq. this irq is limited to priorities 0 throu gh 2. it is disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 base + $2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read qsci0_xmit ipl 0 0 0 0 qspi0_xmit ipl qspi0_rcv ipl gpioa ipl gpiob ipl gpioc ipl write reset 0000000000000000
register descriptions 56f8023 data sheet, rev. 3 freescale semiconductor 61 preliminary 5.6.3.4 qspi 0 receiver full interrupt pr iority level (qspi0_rcv ipl)?bits 7?6 this field is used to set the interru pt priority level for the qspi0 recei ver full irq. this irq is limited to priorities 0 through 2. it is disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.3.5 gpioa interrupt priority level (gpioa ipl)?bits 5?4 this field is used to set the interrupt priority level for the gpioa irq. this irq is limited to priorities 0 through 2. it is disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.3.6 gpiob interrupt priority level (gpiob ipl)?bits 3?2 this field is used to set the interr upt priority level for the gpiob irq. this irq is limited to priorities 0 through 2. it is disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.3.7 gpioc interrupt priority level (gpioc ipl)?bits 1?0 this field is used to set the interr upt priority level for the gpioc irq. this irq is limited to priorities 0 through 2. it is disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.4 interrupt priority register 3 (ipr3) figure 5-6 interrupt prio rity register 3 (ipr3) base + $3 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read i2c_err ipl 0 0 0 0 0 0 0 0 qsci0_rcv ipl qsci0_rer r ipl qsci0_tidl ipl write reset 0 000000000000000
56f8023 data sheet, rev. 3 62 freescale semiconductor preliminary 5.6.4.1 i 2 c error interrupt priority level (i2c_err ipl)?bits 15?14 this field is used to set the in terrupt priority level for the i 2 c error irq. this irq is limited to priorities 0 through 2. it is disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.4.2 reserved?bits 13?6 this bit field is reserved. each bit must be set to 0. 5.6.4.3 qsci 0 receiver full interrupt pr iority level (qsci0 _rcv ipl)?bits 5?4 this field is used to set the interr upt priority level for th e qsci0 receiver full irq. this irq is limited to priorities 0 through 2. it is disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.4.4 qsci 0 receiver error inte rrupt priority leve l (qsci0_rerr ipl)? bits 3?2 this field is used to set the interrupt priority level for the qsci0 receiver error irq. this irq is limited to priorities 0 through 2. it is disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.4.5 qsci 0 transmitter idle i nterrupt priority leve l (qsci0_tidl ipl)? bits 1?0 this field is used to set the interrupt priority level for the qsci0 transmitter idle irq. this irq is limited to priorities 0 through 2. it is disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2
register descriptions 56f8023 data sheet, rev. 3 freescale semiconductor 63 preliminary 5.6.5 interrupt priority register 4 (ipr4) figure 5-7 interrupt prio rity register 4 (ipr4) 5.6.5.1 timer a, channel 3 i nterrupt priority l evel (tmra_3 ipl)? bits 15?14 this field is used to set the interr upt priority level for the timer a, ch annel 3 irq. this irq is limited to priorities 0 through 2. it is disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.5.2 timer a, channel 2 i nterrupt priority l evel (tmra_2 ipl)? bits 13?12 this field is used to set the interr upt priority level for the timer a, ch annel 2 irq. this irq is limited to priorities 0 through 2. it is disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.5.3 timer a, channel 1 i nterrupt priority l evel (tmra_1 ipl)? bits 11?10 this field is used to set the interr upt priority level for the timer a, ch annel 1 irq. this irq is limited to priorities 0 through 2. it is disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 base + $4 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read tmra_3 ipl tmra_2 ipl tmra_1 ipl tmra_0 ipl i2c_stat ipl i2c_tx ipl i2c_rx ipl i2c_gen ipl write reset 0000000000000000
56f8023 data sheet, rev. 3 64 freescale semiconductor preliminary 5.6.5.4 timer a, channel 0 i nterrupt priority l evel (tmra_0 ipl)? bits 9?8 this field is used to set the interr upt priority level for the timer a, ch annel 0 irq. this irq is limited to priorities 0 through 2. it is disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.5.5 i 2 c status interrupt priority l evel (i2c_stat ipl)?bits 7?6 this field is used to set the interrupt priority level for the i 2 c status irq. this irq is limited to priorities 0 through 2. it is disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.5.6 i 2 c transmit interrupt priority level (i2c_tx ipl)?bits 5?4 this field is used to set the in terrupt priority level for the i 2 c transmit irq. this irq is limited to priorities 0 through 2. it is disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.5.7 i 2 c receive interrupt priority le vel (i2c_rx ipl)? bits 3?2 this field is used to set the interrupt priority level for the i 2 c receiver irq. this irq is limited to priorities 0 through 2. it is disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.5.8 i 2 c general call interrupt priority level (i2c_gen ipl)?bits 1?0 this field is used to set the interrupt priority level for the i 2 c general call irq. this irq is limited to priorities 0 through 2. it is disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2
register descriptions 56f8023 data sheet, rev. 3 freescale semiconductor 65 preliminary 5.6.6 interrupt priority register 5 (ipr5) figure 5-8 interrupt prio rity register 5 (ipr6) 5.6.6.1 reserved?bits 15?14 this bit field is reserved. each bit must be set to 0. 5.6.6.2 programmable interval timer 0 interrupt priority level (pit0 ipl)? bits 13?12 this field is used to set the interrupt priority leve l for the programmable interv al timer 0 irq. this irq is limited to priorities 0 thr ough 2. it is disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.6.3 comparator b interru pt priority level (compb ipl)? bits 11?10 this field is used to set the interrupt priority level for the comparator b irq. this irq is limited to priorities 0 through 2. it is disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.6.4 comparator a interru pt priority level (compa ipl)? bits 9?8 this field is used to set the interrupt priority level fo r the comparator irq. this irq is limited to priorities 0 through 2. it is disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.6.5 reserved?bits 7?0 this bit field is reserved. each bit must be set to 0. base + $5 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 pit0 ipl compb ipl compa ipl 0 0 0 0 0 0 0 0 write reset 0000000000000000
56f8023 data sheet, rev. 3 66 freescale semiconductor preliminary 5.6.7 interrupt priority register 6 (ipr6) figure 5-9 interrupt prio rity register 6 (ipr6) 5.6.7.1 reserved?bits 15?12 this bit field is reserved. each bit must be set to 0. 5.6.7.2 pwm fault interrupt priori ty level (pwm_f ipl)?bits 11?10 this field is used to set the interr upt priority level for the pwm fault interrupt irq. this irq is limited to priorities 0 through 2. it is disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.7.3 reload pwm interrupt pri ority level (pwm_rl ipl)?bits 9?8 this field is used to set the interr upt priority level for the reload pwm interrupt irq. this irq is limited to priorities 0 through 2. it is disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.7.4 adc zero crossing interrupt pr iority level (adc_zc ipl)?bits 7?6 this field is used to set the interrupt priority leve l for the adc zero crossing ir q. this irq is limited to priorities 0 through 2. it is disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 base + $6 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 pwm_f ipl pwm_rl ipl adc_zc ipl adcb_cc ipl adca_cc ipl 0 0 write reset 0000000000000000
register descriptions 56f8023 data sheet, rev. 3 freescale semiconductor 67 preliminary 5.6.7.5 adc b conversion comp lete interrupt priority level (adcb_cc ipl)?bits 5?4 this field is used to set the inte rrupt priority level for the adc b conversion comp lete irq. this irq is limited to priorities 0 throu gh 2. it is disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.7.6 adc a conversion comp lete interrupt priority level (adca_cc ipl)?bits 3?2 this field is used to set the interrupt priority le vel for the adc a conversion complete irq. this irq is limited to priorities 0 throu gh 2. it is disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.7.7 reserved?bits 1?0 this bit field is reserved. each bit must be set to 0. 5.6.8 vector base address register (vba) figure 5-10 vector base address register (vba) 5.6.8.1 reserved?bits 15?14 this bit field is reserved. each bit must be set to 0. 5.6.8.2 vector address bus (vab) bits 13?0 the value in this register is used as the upper 14 bits of the interrupt vector vab[20:0]. the lower 7 bits are determined based on the highest priority interrupt and are then a ppended onto vba be fore presenting the full vab to the core. base + $7 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 vector_base_address write reset 000000 0 0 0000 1 1. the 56f8023 resets to a value of 0 x 0000. this corresponds to reset addresses of 0 x 000000. 0000
56f8023 data sheet, rev. 3 68 freescale semiconductor preliminary 5.6.9 fast interrupt match 0 register (fim0) figure 5-11 fast interrupt match 0 register (fim0) 5.6.9.1 reserved?bits 15?6 this bit field is reserved. each bit must be set to 0. 5.6.9.2 fast interrupt 0 vector number (fast inte rrupt 0)?bits 5?0 these values determine which irq will be fast interrupt 0. fast interrupts vector directly to a service routine based on values in the fast interrupt vector address registers without having to go to a jump table first. irqs used as fast interrupts must be set to priority level 2. unexp ected results will occur if a fast interrupt vector is set to any othe r priority. a fast interrupt automa tically becomes the highest-priority level 2 interrupt regardless of its location in the interru pt table prior to being de clared as fast interrupt. fast interrupt 0 has priority over fa st interrupt 1. to determine the v ector number of each irq, refer to the vector table. 5.6.10 fast interrupt 0 vector address low register (fival0) figure 5-12 fast interrupt 0 vect or address low register (fival0) 5.6.10.1 fast interrupt 0 vector address low (fi val0)?bits 15?0 the lower 16 bits of the vector addr ess used for fast interrupt 0. this register is combined with fivah0 to form the 21-bit vector address for fast interrupt 0 defined in the fim0 register. 5.6.11 fast interrupt 0 vector address high register (fivah0) figure 5-13 fast interr upt 0 vector address high register (fivah0) 5.6.11.1 reserved?bits 15?5 this bit field is reserved. each bit must be set to 0. base + $8 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 0 0 0 fast interrupt 0 write reset 0000000000000000 base + $9 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read fast interrupt 0 vector address low write reset 0000000000000000 base + $a 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 0 0 0 0 fast interrupt 0 vector address high write reset 0000000000000000
register descriptions 56f8023 data sheet, rev. 3 freescale semiconductor 69 preliminary 5.6.11.2 fast interrupt 0 vector address high (fi vah0)?bits 4?0 the upper five bits of the vector a ddress used for fast inte rrupt 0. this register is combined with fival0 to form the 21-bit vector address for fast interrupt 0 defined in the fim0 register. 5.6.12 fast interrupt 1 match register (fim1) figure 5-14 fast interrupt 1 match register (fim1) 5.6.12.1 reserved?bits 15?6 this bit field is reserved. each bit must be set to 0. 5.6.12.2 fast interrupt 1 vector number (fast inte rrupt 1)?bits 5?0 these values determine which irq will be fast interrupt 1. fast interrupts vector directly to a service routine based on values in the fast interrupt vector address registers without having to go to a jump table first. irqs used as fast interrupts must be set to priority level 2. unexp ected results will occur if a fast interrupt vector is set to any othe r priority. a fast inte rrupt automatically beco mes the highest priority level 2 interrupt, regardless of its location in the interr upt table prior to being d eclared as fast interrupt. fast interrupt 0 has priority over fast interrupt 1. to determine the vector numbe r of each irq, refer to the vector table. 5.6.13 fast interrupt 1 vector address low register (fival1) figure 5-15 fast interrupt 1 vect or address low register (fival1) 5.6.13.1 fast interrupt 1 vector address low (fi val1)?bits 15?0 the lower 16 bits of the vector addr ess used for fast interrupt 1. this register is combined with fivah1 to form the 21-bit vector address for fast interrupt 1 defined in the fim1 register. base + $b 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 0 0 0 fast interrupt 1 write reset 0000000000000000 base + $c 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read fast interrupt 1 vector address low write reset 0000000000000000
56f8023 data sheet, rev. 3 70 freescale semiconductor preliminary 5.6.14 fast interrupt 1 vector address high (fivah1) figure 5-16 fast interr upt 1 vector address high register (fivah1) 5.6.14.1 reserved?bits 15?5 this bit field is reserved. each bit must be set to 0. 5.6.14.2 fast interrupt 1 vector address high (fi vah1)?bits 4?0 the upper five bits of the vector a ddress used for fast inte rrupt 1. this register is combined with fival1 to form the 21-bit vector address for fast interrupt 1 defined in the fim1 register. 5.6.15 irq pending register 0 (irqp0) figure 5-17 irq pending register 0 (irqp0) 5.6.15.1 irq pending (pending)?bits 16?2 these register bit va lues represent the pending irqs for inte rrupt vector numbers 2 through 16. ascending irq numbers correspond to ascending bit locations. ? 0 = irq pending for this vector number ? 1 = no irq pending for this vector number 5.6.15.2 reserved?bit 0 this bit field is reserved. it must be set to 1. 5.6.16 irq pending register 1 (irqp1) figure 5-18 irq pending register 1 (irqp1) base + $d 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 0 0 0 0 fast interrupt 1 vector address high write reset 0000000000000000 base + $e 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read pending[16:2] 1 write reset 1111111111111111 base + $f 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read pending[32:17] write reset 1111111111111111
register descriptions 56f8023 data sheet, rev. 3 freescale semiconductor 71 preliminary 5.6.16.1 irq pending (pending)?bits 32?17 these register bit values repr esent the pending irqs for interr upt vector numbe rs 17 through 32. ascending irq numbers correspond to ascending bit locations. ? 0 = irq pending for this vector number ? 1 = no irq pending for this vector number 5.6.17 irq pending register 2 (irqp2) figure 5-19 irq pending register 2 (irqp2) 5.6.17.1 irq pending (pending)?bits 48?33 this register bit values represent the pending irqs for interrupt vector numbers 33 through 48. ascending irq numbers correspond to ascending bit locations. ? 0 = irq pending for this vector number ? 1 = no irq pending for this vector number 5.6.18 irq pending register 3 (irqp3) figure 5-20 irq pending register 3 (irqp3) 5.6.18.1 irq pending (pending)?bits 63?49 these register bit values repr esent the pending irqs for interr upt vector numbe rs 49 through 63. ascending irq numbers correspond to ascending bit locations. ? 0 = irq pending for this vector number ? 1 = no irq pending for this vector number 5.6.19 interrupt contro l register (ictrl) figure 5-21 interrupt control register (ictrl) base + $10 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read pending[48:33] write reset 1111111111111111 base + $11 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read pending[63:49] write reset 1111111111111111 $base + $16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read int ipic vab int_ dis 1 1 1 0 0 write reset 0000000000011100
56f8023 data sheet, rev. 3 72 freescale semiconductor preliminary 5.6.19.1 interrupt (int)?bit 15 this read-only bit reflects the state of th e interrupt to the 56800e core. ? 0 = no interrupt is be ing sent to the 56800e core ? 1 = an interrupt is be ing sent to the 56800e core 5.6.19.2 interrupt priority level (ipic)?bits 14?13 these read-only bits reflect the state of the new interrupt priority level bits be ing presented to the 56800e core. these bits indicate the priority level needed fo r a new irq to interrupt the current interrupt being sent to the 56800e core. this field is only updated wh en the 56800e core jumps to a new interrupt service routine. note: nested interrupts may cause this field to be update d before the original inte rrupt service routine can read it. ? 00 = required nested exception prio rity levels are 0, 1, 2, or 3 ? 01 = required nested exception pr iority levels are 1, 2, or 3 ? 10 = required nested exceptio n priority levels are 2 or 3 ? 11 = required nested exception priority level is 3 5.6.19.3 vector number - vec tor address bus (vab)?bits 12?6 this read-only field shows bits [7:1] of the vector address bus used at th e time the last irq was taken. in the case of a fast interrupt, it s hows the lower address bits of the jump address. this field is only updated when the 56800e core jumps to a new interrupt service routine. note: nested interrupts may cause this field to be update d before the original inte rrupt service routine can read it. 5.6.19.4 interrupt disable (int_dis)?bit 5 this bit allows all interrupts to be disabled. ? 0 = normal operation (default) ? 1 = all interrupts disabled table 5-4 interrupt priority encoding ipic_value[1:0] current interrupt priority level required nested exception priority 00 no interrupt or swilp priorities 0, 1, 2, 3 01 priority 0 priorities 1, 2, 3 10 priority 1 priorities 2, 3 11 priority 2 or 3 priority 3
resets 56f8023 data sheet, rev. 3 freescale semiconductor 73 preliminary 5.6.19.5 reserved?bits 4-2 this bit field is reserved. each bit must be set to 1. 5.6.19.6 reserved?bits 1?0 this bit field is reserved. each bit must be set to 0. 5.7 resets 5.7.1 general 5.7.2 description of reset operation 5.7.2.1 reset handshake timing the itcn provides the 56800e core with a reset vector address on the vab pins whenever reset is asserted from the sim. th e reset vector will be pr esented until the second risi ng clock edge after reset is released. the genera l timing is shown in figure 5-22 . figure 5-22 reset interface 5.7.3 itcn after reset after reset, all of the itcn regist ers are in their default states. this means all interrupts are disabled, except the core irqs wi th fixed priorities: ? illegal instruction ? sw interrupt 3 ? hw stack overflow ? misaligned long word access ? sw interrupt 2 table 5-5 reset summary reset priority source characteristics core reset rst core reset from the sim res clk vab pab reset_vector_adr read_adr
56f8023 data sheet, rev. 3 74 freescale semiconductor preliminary ? sw interrupt 1 ? sw interrupt 0 ? sw interrupt lp these interrupts are enabled at their fixed priority levels. part 6 system integration module (sim) 6.1 introduction the sim module is a system catchall for the glue logic that ties together the system-on-chip. it controls distribution of resets and clocks and provides a number of control features. the system integration module?s functions are discussed in mo re detail in the following sections. 6.2 features the sim has the following features: ? chip reset sequencing ? core and peripheral clock control and distribution ? stop/wait mode control ? system status control ? registers containing the jtag id of the chip ? controls for programmable peripheral and gpio connections ? peripheral clocks for tmr and pwm with a high-speed (3x) option ? power-saving clock gating for peripherals ? three power modes (run, wait, st op) to control power utilization ? stop mode shuts down the 56800e core, system clock, and peripheral clock ? wait mode shuts down the 56800e core and unnecessary system clock operation ? run mode supports full device operation ? controls the enable/disable functions of the 56800e core wait and stop instructions with write protection capability ? controls the enable/disable functio ns of large regulator standby mode with write protection capability ? permits selected peripherals to run in stop mode to gene rate stop recovery interrupts ? controls for programmable peripheral and gpio connections ? software chip reset ? i/o short address ba se location control ? peripheral protection control to provide runaway code protectio n for safety-critical applications ? controls output of internal clock sources to clko pin ? four general-purpose software control registers are reset only at power-on ? peripherals stop mode clocking control
register descriptions 56f8023 data sheet, rev. 3 freescale semiconductor 75 preliminary 6.3 register descriptions a write to an address without an associated register is an nop. a read from an address without an associated register returns unknown data. table 6-1 sim register s (sim_base = $00 f100) register acronym base address + register name section location ctrl $0 control register 6.3.1 rstat $1 reset status register 6.3.2 swc0 $2 software control register 0 6.3.3 swc1 $3 software control register 1 6.3.3 swc2 $4 software control register 2 6.3.3 swc3 $5 software control register 3 6.3.3 mshid $6 most significant half of jtag id 6.3.4 lshid $7 least significant half of jtag id 6.3.5 pwr $8 power control register 6.3.6 reserved clkout $a clko se lect register 6.3.7 pcr $b peripheral clock rate register 6.3.8 pce0 $c peripheral clock enable register 0 6.3.9 pce1 $d peripheral clock enable register 0 6.3.10 sd0 $e stop disable register 0 6.3.11 sd1 $f stop disable register 1 6.3.12 iosahi $10 i/o short address location high register 6.3.13 iosalo $11 i/o short address location low register 6.3.14 prot $12 protection register 6.3.15 gpsa0 $13 gpio peripheral sele ct register 0 for gpioa 6.3.16 reserved gpsb0 $15 gpio peripheral sele ct register 0 for gpiob 6.3.17 gpsb1 $16 gpio peripheral sele ct register 1 for gpiob 6.3.18 reserved iss0 $18 internal source select register 0 for pwm 6.3.19 iss1 $19 internal source select register 1 for dacs 6.3.20 iss2 $1a internal source select register 2 for quad timer a 6.3.21 reserved
56f8023 data sheet, rev. 3 76 freescale semiconductor preliminary figure 6-1 sim register map summary add. offset address acronym 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 $0 sim_ ctrl r 0 0 0 0 0 0 0 0 0 0 once ebl 0 sw rst stop_ disable wait_ disable w $1 sim_ rstat r 0 0 0 0 0 0 0 0 0 swr cop_ tor cop_ lor extr por 0 0 w $2 sim_swc0 r software control data 0 w $3 sim_swc1 r software control data 1 w $4 sim_swc2 r software control data 2 w $5 sim_swc3 r software control data 3 w $6 sim_mshid r 0 0 0 0 0 001 1 1110010 w $7 sim_lshid r 1 0 0 0 0 000 0 0011101 w $8 sim_pwr r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 lrstdby w reserved $a sim_ clkout r 0 0 0 0 0 0 pwm 3pwm 2pwm 1pwm 0 clk dis clkosel 0 w $b sim_pcr r 0 tmra_ cr pwm_c r i2c_ cr 0 0 0 0 0 0 0 0 0 0 0 0 w $c sim_pce0 r cmpb cmpa dac1 dac0 0 adc 0 0 0 i2c 0 qsci0 0 qspi0 0 pwm w $d sim_pce1 r 0 0 0 pit0 0 0 0 0 0 0 0 0 ta3 ta2 ta1 ta0 w $e sim_sd0 r cmpb_ sd cmpa_ sd dac1_ sd dac0_ sd 0 adc_ sd 0 0 0 i2c_ sd 0 qsci0 _sd 0 qspi0 _sd 0 pwm_ sd w $f sim_sd1 r 0 0 0 pit0_ sd 0 0 0 0 0 0 0 0 ta3_ sd ta2_ sd ta1_ sd ta0_ sd w $10 sim_iosahi r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 isal[23:22] w $11 sim_iosalo r isal[21:6] w $12 sim_prot r 0 0 0 0 0 0 0 0 0 0 0 0 pcep gipsp w $13 sim_gpsa0 r 0 0 0 gps_ a6 gps_a5 gps_a4 0 0 0 0 0 0 0 0 w reserved $15 sim_gpsb0 r 0 gps_b6 gps_b5 gps_b4 gps_b3 gps_b2 0 gps_ b1 0 gps_ b0 w $16 sim_gpsb1 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 gps_ b7 w reserved $18 sim_ips0 r 0 0 ips0_ fault2 0 ips0_ fault1 0 0 ips0_psrc2 ips0_psrc1 ips0_psrc0 w $19 sim_ips1 r 0 0 0 0 0 0 0 0 0 0 0 0 0 ips1_dsync0 w $1a sim_ips2 r 0 0 0 ips2_ ta3 0 0 0 ips2_ ta2 0 0 0 ips2_ ta1 0 0 0 0 w reserved 0 = read as 0 1 = read as 1 = reserved
register descriptions 56f8023 data sheet, rev. 3 freescale semiconductor 77 preliminary 6.3.1 sim control register (sim_ctrl) figure 6-2 sim control register (sim_ctrl) 6.3.1.1 reserved?bits 15?6 this bit field is reserved. each bit must be set to 0. 6.3.1.2 once enable (onceebl)?bit 5 ? 0 = once clock to 56800e core en abled when core tap is enabled ? 1 = once clock to 56800e core is always enabled note: using default state ?0? is recommended. 6.3.1.3 software reset (swrst)?bit 4 ? writing 1 to this field will cause the device to reset ? read is zero 6.3.1.4 stop disable (s top_disable)?bits 3?2 ? 00 = stop mode will be entered when the 56800e core executes a stop instruction ? 01 = the 56800e stop instruction will not cause entry into stop mode ? 10 = stop mode will be entered when the 5680 0e core executes a stop instruction and the stop_disable field is write-protected until the next reset ? 11 = the 56800e stop instruction will not cause entry into stop mode and the stop_disable field is write-protected until the next reset 6.3.1.5 wait disable (wait_disable)?bits 1?0 ? 00 = wait mode will be entered when th e 56800e core executes a wait instruction ? 01 = the 56800e wait instructio n will not cause entry into wait mode ? 10 = wait mode will be entered when the 568 00e core executes a wait instruction and the wait_disable field is write-p rotected until the next reset ? 11 = the 56800e wait instruction will not cause entry into wait mode and the wait_disable field is write-protected until the next reset 6.3.2 sim reset status register (sim_rstat) this read-only register is updated upon any system reset and indicates th e cause of the most recent reset. it indicates whether the cop reset vector or regular rese t vector (including power-on reset, external reset, software reset) in the vect or table is used. this register is asynchronously reset during power-on reset and subsequently is synchronously updated base d on the precedence level of reset inputs. only the base + $0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 0 0 0 once ebl sw rst stop_ disable wait_ disable write reset 0000000000000000
56f8023 data sheet, rev. 3 78 freescale semiconductor preliminary most recent reset source will be indicated if mult iple resets occur. if multiple reset sources assert simultaneously, the highest-preceden ce source will be indicated. the pr ecedence from highest to lowest is power-on reset, external reset, cop loss of re ference reset, cop time-o ut reset, and software reset. power-on reset is always set during a power-on reset; howev er, power-on reset will be cleared and external reset will be set if the external reset pin is asserted or remains asserted after the power-on reset has deasserted. figure 6-3 sim reset status register (sim_rstat) 6.3.2.1 reserved?bits 15?7 this bit field is reserved. each bit must be set to 0. 6.3.2.2 software reset (swr)?bit 6 when set, this bit indicates that the previous system reset occurred as a result of a softwa re reset (written 1 to swrst bit in the sim_ctrl register). 6.3.2.3 cop time-out reset (cop_tor)?bit 5 when set, this bit indicates that the previous syst em reset was caused by the computer operating properly (cop) module signaling a cop time-out reset. if cop_to r is set as code starts executing, the cop reset vector in the vector table w ill be used. otherwise, the normal reset vector is used. 6.3.2.4 cop loss of refere nce reset (cop_lor)?bit 4 when set, this bit indicates that the previous syst em reset was caused by the computer operating properly (cop) module signaling a loss of cop reference clock reset. if cop_lor is set as code starts executing, the cop reset vector in the vector table will be used. otherwise, the normal reset vector is used. 6.3.2.5 external reset (extr)?bit 3 when set, this bit indicates that the previous system reset was caused by an external reset. 6.3.2.6 power-on reset (por)?bit 2 this bit is set during a power-on reset. 6.3.2.7 reserved?bits 1?0 this bit field is reserved. each bit must be set to 0. base + $1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 0 0 swr cop_ tor cop_ lor extr por 0 0 write reset 00000000000 0 0100
register descriptions 56f8023 data sheet, rev. 3 freescale semiconductor 79 preliminary 6.3.3 sim software control registers (sim_swc0, sim_swc1, sim_swc2, and sim_swc3) these registers are general-purpose registers. they are reset only at power-on, so they can monitor software execution flow. figure 6-4 sim software contro l register 0 (sim_swc0 - 3) 6.3.3.1 software control register 0 - 3 (field)?bits 15?0 this register is reset only by the po wer-on reset (por). it is intende d for use by a software developer to contain data that will be unaffected by the other reset sources (ext ernal reset, software reset, and cop reset). 6.3.4 most significant half of jtag id (sim_mshid) this read-only register displays the most significant half of the jtag id for the ch ip. this register reads $01f2. figure 6-5 most significant half of jtag id (sim_mshid) 6.3.5 least significant half of jtag id (sim_lshid) this read-only register displays th e least significant half of the jtag id for the chip. this register reads $801d. figure 6-6 least significant half of jtag id (sim_lshid) base + $2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read software control data 0 - 3 write reset 0 0 0 0 0 0 0 0000 0 0000 base + $6 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 1111 1 0010 write reset 0 0 0 0 0 0 0 1111 1 0010 base + $7 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 1 0 0 0 0 0 0 0000 1 1101 write reset 1 0 0 0 0 0 0 0000 1 1101
56f8023 data sheet, rev. 3 80 freescale semiconductor preliminary 6.3.6 sim power control register (sim_pwr) this register controls the standby mode of the large on-chip regulator. the large on-chip regulator derives the core digital logic power supply from the io power supply. at a sy stem bus frequency of 200khz, the large regulator may be put in a reduced-power sta ndby mode without interfering with device operation to reduce device power consumption. re fer to the overview of power-down modes and the overview of clock generation for more information on th e use of large regulator standby. figure 6-7 sim power cont rol register (sim_pwr) 6.3.6.1 reserved?bits 15?2 this bit field is reserved. each bit must be set to 0. 6.3.6.2 large regulator sta ndby mode[1:0] (lrstdby)?bits 1?0 ? 00 = large regulator is in normal mode ? 01 = large regulator is in standby (reduced-power) mode ? 10 = large regulator is in normal mode and the lr stdby field is write-protected until the next reset ? 11 = large regulator is in standby mode and the lrstdby field is write-protected until the next reset 6.3.7 clock output sele ct register (sim_clkout) the clock output select register can be used to multiplex out selected clock sources generated inside the clock generation and sim modules onto the muxed clock output pins. all functionality is for test purposes only. glitches may be produced when the clock is enabled or switche d. the delay from the clock source to the output is unspecified. the obser vability of the clko clock output signal at an output pad is subject to the frequency limitations of the associated io cell. gpioa[3:0] can function as gpio, pwm, or as clock output pins. if gpioa[3:0] are programmed to operate as peripheral outputs, then the choice is between pw m and clock outputs. the default state is for the peripheral function of gpioa[3: 0] to be programmed as pwm (sel ected by bits [9:6] of the clock output select register). gpiob4 can function as gpio, or as other peripheral outputs, includi ng clock output (clko). if gpiob4 is programmed to operate as a pe ripheral output and clko is selected in the sim_gpsb0 register, bits [4:0] decide if clko is enabled or disabled and which clock source is selected if clko is enabled. see figure 6-8 for details. base + $8 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 0 0 0 0 0 0 0 lrstdby write reset 0000000000000000
register descriptions 56f8023 data sheet, rev. 3 freescale semiconductor 81 preliminary figure 6-8 clko select register (sim_clkout) 6.3.7.1 reserved?bits 15?10 this bit field is reserved. each bit must be set to 0. 6.3.7.2 pwm 3?bit 9 ? 0 = peripheral output function of gpioa[3] is defined to be pwm 3 ? 1 = peripheral output function of gpioa[3] is defined to be the relaxation oscillator clock 6.3.7.3 pwm 2?bit 8 ? 0 = peripheral output function of gpioa[2] is defined to be pwm 2 ? 1 = peripheral output function of gpioa[2] is defined to be the system clock 6.3.7.4 pwm 1?bit 7 ? 0 = peripheral output function of gpioa[1] is defined to be pwm 1 ? 1 = peripheral output function of gpioa[1] is defined to be 2x system clock 6.3.7.5 pwm 0?bit 6 ? 0 = peripheral output function of gpioa[0] is defined to be pwm 0 ? 1 = peripheral output function of gpioa[0] is defined to be 3x system clock 6.3.7.6 clockout disable (clkdis)?bit 5 ? 0 = clkout output function is enabled and will output the signal indicated by clkosel ? 1 = clkout output function is disabled 6.3.7.7 clockout select (clkosel)?bits 4?0 clkosel selects the clock to be m uxed out on the clko pin as defined in the following. internal delay to clko output is unspecified. signal at the out put pad is undefined when clko signal frequency exceeds the rated frequency of th e i/o cell. clko may not operate as expected when clkdis and clkosel settings are changed. ? 00000 = continuous system clock ? 00001 = continuous peripheral clock ? 00010 = 3x system clock ? 00100..... 11111 = reserved for factory test base + $a 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 pwm 3pwm 2pwm 1pwm 0 clk dis clkosel write reset 0 0 0 0 0 0 0 0 0 0 1 00000
56f8023 data sheet, rev. 3 82 freescale semiconductor preliminary 6.3.8 peripheral clock ra te register (sim_pcr) by default, all peripherals are clocked at the system clock rate, which has a maximum of 32mhz. selected peripherals clocks have th e option to be clocked at 3x system cl ock rate, which has a maximum of 96mhz, if the pll output clock is selected as the system clock. if pll is disa bled, the 3x system clock will not be available. this register is used to enable high- speed clocking for those pe ripherals that support it. note: operation is unpredictable if peripheral clocks are reconfigured at runtime, so peripherals should be disabled before a peripheral clock is reconfigured. figure 6-9 peripheral clock rate register (sim_pcr) 6.3.8.1 reserved?bit 15 this bit field is reserved. it must be set to 0. 6.3.8.2 quad timer a clock rate (tmra_cr)?bit 14 this bit selects the clock speed for the quad timer a module. ? 0 = quad timer a clock rate equals the sy stem clock rate, to a maximum 32mhz (default) ? 1 = quad timer a clock rate equals 3x system clock rate, to a maximum 96mhz 6.3.8.3 pulse width modulator clock rate (pwm_cr)?bit 13 this bit selects the clock speed for the pwm module. ? 0 = pwm module clock rate equals the system clock rate, to a maximum 32mhz (default) ? 1 = pwm module clock rate equals 3x system clock rate, to a maximum 96mhz 6.3.8.4 inter-integrated circui t run clock rate (i2c_cr)?bit 12 this bit selects the clock speed for the i 2 c run clock. ?0 = i 2 c module run clock rate equals the system clock rate, to a maximum 32mhz (default) ?1 = i 2 c module run clock rate equals 3x system clock rate, to a maximum 96mhz 6.3.8.5 reserved?bits 11?0 this bit field is reserved. each bit must be set to 0. 6.3.9 peripheral clock enable register 0 (sim_pce0) the peripheral clock enable register enables or disables clocks to the peripherals as a power savings feature. significant power savings are achieved by enabling only the peripheral clocks that are in use. base + $b 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 tmra_ cr pwm_ cr i2c_ cr 0 0 0 0 0 0 0 0 0 0 0 0 write reset 0 0 0000 0 0 00000000
register descriptions 56f8023 data sheet, rev. 3 freescale semiconductor 83 preliminary when a peripheral?s clock is disable d, that peripheral is in stop mode. accesses made to a module that has its clock disabled will ha ve no effect. the corresponding peripheral should itself be disabled while its clock is shut off. ipbus writes are not possible. setting the pce bit does not guarantee that the pe ripheral?s clock is running. enabled peripheral clocks will still become disabl ed in stop mode, unless the periphe ral?s stop disable control in the sd n register is set to 1. figure 6-10 peripheral clock en able register 0 (sim_pce0) 6.3.9.1 comparator b clock enable (cmpb)?bit 15 ? 0 = the clock is not provided to the comparator b module (the comparator b module is disabled) ? 1 = the clock is enabled to the comparator b module 6.3.9.2 comparator a clock enable (cmpa)?bit 14 ? 0 = the clock is not provided to the comparator a module (the comparator a module is disabled) ? 1 = the clock is enabled to the comparator a module 6.3.9.3 digital-to-analog cl ock enable 1 (dac1)?bit 13 ? 0 = the clock is not provided to the da c1 module (the dac1 module is disabled) ? 1 = the clock is enabled to the dac1 module 6.3.9.4 digital-to-analog cl ock enable 0 (dac0)?bit 12 ? 0 = the clock is not provided to the da c0 module (the dac0 module is disabled) ? 1 = the clock is enabled to the dac0 module 6.3.9.5 reserved?bit 11 this bit field is reserved. it must be set to 0. 6.3.9.6 analog-to-digital conver ter clock enable (adc)?bit 10 ? 0 = the clock is not provided to the adc module (the adc module is disabled) ? 1 = the clock is enabled to the adc module 6.3.9.7 reserved?bits 9?7 this bit field is reserved. each bit must be set to 0. 6.3.9.8 inter-integrated circui t ipbus clock enable (i2c)?bit 6 ? 0 = the clock is not provided to the i 2 c module (the i 2 c module is disabled) base + $c 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read cmpb cmpa dac1 dac0 0 adc 0 0 0 i2c 0 qsci0 0 qspi0 0 pwm write reset 0 0 0 0 000 0 00 0 0 0 0 0 0
56f8023 data sheet, rev. 3 84 freescale semiconductor preliminary ? 1 = the clock is enabled to the i 2 c module 6.3.9.9 reserved?bit 5 this bit field is reserved. it must be set to 0. 6.3.9.10 qsci 0 clock enable (qsci0)?bit 4 ? 0 = the clock is not provided to the qsci0 module (the qsci0 module is disabled) ? 1 = the clock is enabled to the qsci0 module 6.3.9.11 reserved?bit 3 this bit field is reserved. it must be set to 0. 6.3.9.12 qspi 0 clock enable (qspi0)?bit 2 ? 0 = the clock is not provided to the qs pi0 module (the qspi0 module is disabled) ? 1 = the clock is enabled to the qspi0 module 6.3.9.13 reserved?bit 1 this bit field is reserved. it must be set to 0. 6.3.9.14 pwm clock enable (pwm)?bit 0 ? 0 = the clock is not provided to the pwm module (the pwm module is disabled) ? 1 = the clock is enabled to the pwm module 6.3.10 peripheral clock enab le register 1 (sim_pce1) see section 6.3.9 for general information about pe ripheral clock enable registers. figure 6-11 peripheral clock en able register 1 (sim_pce1) 6.3.10.1 reserved?bit 15 - 13 this bit field is reserved. each bit must be set to 0. 6.3.10.2 programmable interval ti mer 0 clock enable (pit0)?bit 12 ? 0 = the clock is not provided to the pit0 module (the pit0 module is disabled) ? 1 = the clock is enabled to the pit0 module 6.3.10.3 reserved?bits 11?4 this bit field is reserved. each bit must be set to 0. base + $d 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 pit0 0 0 0 0 0 0 0 0 ta3 ta2 ta1 ta0 write reset 0000000 0 00000 0 0 0
register descriptions 56f8023 data sheet, rev. 3 freescale semiconductor 85 preliminary 6.3.10.4 quad timer a, channel 3 clock enable (ta3)?bit 3 ? 0 = the clock is not provided to the timer a3 module (the timer a3 module is disabled) ? 1 = the clock is enable d to the timer a3 module 6.3.10.5 quad timer a, channel 2 clock enable (ta2)?bit 2 ? 0 = the clock is not provided to the timer a2 module (the timer a2 module is disabled) ? 1 = the clock is enable d to the timer a2 module 6.3.10.6 quad timer a, channel 1 clock enable (ta1)?bit 1 ? 0 = the clock is not provided to the timer a1 module (the timer a1 module is disabled) ? 1 = the clock is enable d to the timer a1 module 6.3.10.7 quad timer a, channel 0 clock enable (ta0)?bit 0 ? 0 = the clock is not provided to the timer a0 module (the timer a0 module is disabled) ? 1 = the clock is enable d to the timer a0 module 6.3.11 stop disable register 0 (sd0) by default, peripheral cl ocks are disabled during stop mode in order to maximize power savings. this register will allow an indi vidual peripheral to operate in stop mode. since asserti ng an interrupt causes the system to return to run mode, this feature is provided so th at selected peripherals can be left operating in stop mode for the purpose of generating a wake-up interrupt. for power-conscious applications, it is recommended that only a minimum set of peripherals be configured to remain operational during stop mode. peripherals should be put in a non-operating (disabled) configuration prior to entering stop mode unless their corresponding stop disable cont rol is set to 1. refer to the 56f802x and 56f803x peripheral reference manual for further details. r eads and writes cannot be made to a module that has its clock disabled. figure 6-12 stop disabl e register 0 (sd0) 6.3.11.1 comparator b clock stop disable (cmpb_sd)?bit 15 ? 0 = the clock is disabled during stop mode ? 1 = the clock is enabled during stop mode if the cl ock to this peripheral is enabled in the sim_pce0 register base + $e 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read cmpb_ sd cmpa_ sd dac1 _sd dac0_ sd 0 adc_ sd 0 0 0 i2c_ sd 0 qsci0_ sd 0 qspi0_ sd 0 pwm_ sd write reset 0 0 0 0 000 0000 0 0 0 0 0
56f8023 data sheet, rev. 3 86 freescale semiconductor preliminary 6.3.11.2 comparator a clock stop disable (cmpa_sd)?bit 14 ? 0 = the clock is disabled during stop mode ? 1 = the clock is enabled during stop mode if the cl ock to this peripheral is enabled in the sim_pce0 register 6.3.11.3 digital-to-analog converter 0 clock stop disable (dac1_sd)?bit 13 ? 0 = the clock is disabled during stop mode ? 1 = the clock is enabled during stop mode if the cl ock to this peripheral is enabled in the sim_pce0 register 6.3.11.4 digital-to-analog converter 0 clock stop disable (dac0_sd)?bit 12 ? 0 = the clock is disabled during stop mode ? 1 = the clock is enabled during stop mode if the cl ock to this peripheral is enabled in the sim_pce0 register 6.3.11.5 reserved?bit 11 this bit field is reserved. it must be set to 0. 6.3.11.6 analog-to-digital converte r clock stop disable (adc_sd)?bit 10 ? 0 = the clock is disabled during stop mode ? 1 = the clock is enabled during stop mode if the cl ock to this peripheral is enabled in the sim_pce0 register 6.3.11.7 reserved?bits 9?7 this bit field is reserved. each bit must be set to 0. 6.3.11.8 inter-integrated circuit clock stop disable (i2c_sd)?bit 6 ? 0 = the clock is disabled during stop mode ? 1 = the clock is enabled during stop mode if the cl ock to this peripheral is enabled in the sim_pce0 register 6.3.11.9 reserved?bit 5 this bit field is reserved. it must be set to 0. 6.3.11.10 qsci0 clock stop disable (qsci0_sd)?bit 4 ? 0 = the clock is disabled during stop mode ? 1 = the clock is enabled during stop mode if the cl ock to this peripheral is enabled in the sim_pce0 register 6.3.11.11 reserved?bit 3 this bit field is reserved. it must be set to 0.
register descriptions 56f8023 data sheet, rev. 3 freescale semiconductor 87 preliminary 6.3.11.12 qspi0 clock stop disable (qspi0_sd)?bit 2 each bit controls clocks to the indicated peripheral. ? 0 = the clock is disabled during stop mode ? 1 = the clock is enabled during stop mode if the cl ock to this peripheral is enabled in the sim_pce0 register 6.3.11.13 reserved?bit 1 this bit field is reserved. it must be set to 0. 6.3.11.14 pwm clock stop disable (pwm_sd)?bit 0 ? 0 = the clock is disabled during stop mode ? 1 = the clock is enabled during stop mode if the cl ock to this peripheral is enabled in the sim_pce0 register 6.3.12 stop disable register 1 (sd1) see section 6.3.11 for general information a bout stop disable registers. figure 6-13 stop disabl e register 1 (sd1) 6.3.12.1 reserved?bit 15-13 this bit field is reserved. each bit must be set to 0. 6.3.12.2 programmable interval timer 0 clock stop disable (pit0_sd)?bit 12 ? 0 = the clock is disabled during stop mode ? 1 = the clock is enabled during stop mode if the cl ock to this peripheral is enabled in the sim_pce1 register 6.3.12.3 reserved?bits 11?4 this bit field is reserved. each bit must be set to 0. 6.3.12.4 quad timer a, channel 3 clock stop disable (ta3_sd)?bit 3 ? 0 = the clock is disabled during stop mode ? 1 = the clock is enabled during stop mode if the cl ock to this peripheral is enabled in the sim_pce1 register base + $f 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 pit0_ sd 0 0 0 0 0 0 0 0 ta3_ sd ta2_ sd ta1_ sd ta0_ sd write reset 000 0000000 000000
56f8023 data sheet, rev. 3 88 freescale semiconductor preliminary 6.3.12.5 quad timer a, channel 2 clock stop disable (ta2_sd)?bit 2 ? 0 = the clock is disabled during stop mode ? 1 = the clock is enabled during stop mode if the cl ock to this peripheral is enabled in the sim_pce1 register 6.3.12.6 quad timer a, channel 1 clock stop disable (ta1_sd)?bit 1 ? 0 = the clock is disabled during stop mode ? 1 = the clock is enabled during stop mode if the cl ock to this peripheral is enabled in the sim_pce1 register 6.3.12.7 quad timer a, channel 0 clock stop disable (ta0_sd)?bit 0 ? 0 = the clock is disabled during stop mode ? 1 = the clock is enabled during stop mode if the cl ock to this peripheral is enabled in the sim_pce1 register 6.3.13 i/o short address locatio n register high (sim_iosahi) in i/o short address mode, the inst ruction specifies only 6 lsbs of the effective address; the upper 18 bits are ?hard coded? to a specific area of memory. this scheme allows efficient access to a 64-location area in peripheral space with single word instruction. s hort address location regist ers specify the upper 18 bits of i/o address, which are ?hard coded?. these regist ers allow access to peripheral s using i/o short address mode, regardless of the physical loca tion of the peripheral, as shown in figure 6-14 . figure 6-14 i/o short address determination with this register set, software can set the sim_iosahi and sim_io salo registers to point to its peripheral registers and then use the i/o short addressing mode to access them. note: the default value of this register set points to the eonce registers. note: the pipeline delay between setting this register set and using shor t i/o addressing with the new value is five instruction cycles. instruction portion ? hard coded? address portion 6 bits from i/o short address mode instruction 16 bits from sim_iosalo register 2 bits from sim_iosahi register full 24-bit for short i/o address
register descriptions 56f8023 data sheet, rev. 3 freescale semiconductor 89 preliminary figure 6-15 i/o short address locat ion high register (sim_iosahi) 6.3.13.1 reserved?bits 15?2 this bit field is reserved. each bit must be set to 0. 6.3.13.2 input/output short addres s location (isal[23:22])?bits 1?0 this field represents the upper two address bi ts of the ?hard code d? i/o short address. 6.3.14 i/o short address locat ion register low (sim_iosalo) see section 6.3.13 for general information about i/ o short address location registers. figure 6-16 i/o short address locat ion low register (sim_iosalo) 6.3.14.1 input/output short addres s location (isal[2 1:6])?bits 15?0 this field represents the lower 16 address bi ts of the ?hard code d? i/o short address. 6.3.15 protection register (sim_prot) this register provides write protec tion of selected contro l fields for safety-cr itical applications. the primary purpose is to prevent uns afe conditions due to the unintenti onal modification of these fields between the onset of a code runa way and a reset by the co p watchdog. the gpio an d internal peripheral select protection (gipsp) field protect s the contents of registers in the sim and gpio modules that control inter-peripheral signal muxing and gpio configuration. the periphera l clock enable protection (pcep) field protects the sim registers? contents, which contain peripheral cloc k controls. some peripherals provide additional safety features. refer to the 56f802x and 56f803x peripheral reference manual for details. flexibility is provided so that write protection control values may themselves be optionally locked (write-protected). protection controls in this register have two bit values which de termine the setting of the control and whether the value is locked. while a protection control remains unlocked, protection can be disabled and re-enabled by software. once a protection control is lo cked, its value can only be altered by a chip reset, which restores its default non-locked value. base + $10 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 0 0 0 0 0 0 0 isal[23:22] write reset 000000 0 0 0000 0 0 11 base + $11 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read isal[21:6] write reset 111111 1 1 1111 1 1 11
56f8023 data sheet, rev. 3 90 freescale semiconductor preliminary figure 6-17 protection register (sim_prot) 6.3.15.1 reserved?bits 15?4 this bit field is reserved. each bit must be set to 0. 6.3.15.2 peripheral clock enable protection (pcep)?bits 3?2 these bits enable write protect ion of all fields in the pce n , sd n , and pcr registers in the sim module. ? 00 = write protection off (default) ? 01 = write protection on ? 10 = write protection off and locked until chip reset ? 11 = write protection on and locked until chip reset 6.3.15.3 gpio and internal periphera l select protection (gipsp)?bits 1?0 these bits enable wr ite protection of gps n and ips n registers in the sim m odule and write protect all gpio x _peren, gpio x _ppoutm and gpio x _drive registers in gpio modules. ? 00 = write protection off (default) ? 01 = write protection on ? 10 = write protection off and locked until chip reset ? 11 = write protection on and locked until chip reset note: the pwm fields in the clkout register are also wr ite protected by gipsp. they are reserved for in-house test only. 6.3.16 sim gpio peripheral select register 0 for gpioa (sim_gpsa0) most i/o pins have an associated gpio function. in addition to the gpio func tion, i/o can be configured to be one of several pe ripheral functions. the gpio x _peren register within the gpio module controls the selection between periphe ral or gpio control of th e i/o pins. the gpio functi on is selected when the gpio x _peren bit for the i/o is 0. when the gpio x _peren bit of the gpio is 1, the fields in the gps n registers select which peripheral function has control of the i/o. figure 6-18 illustrates the output path to an i/o pin when an i/o has two peripheral functions. s imilar muxing is require d on peripheral function inputs to receive input from the properly selected i/o pin. base + $12 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 0 0 0 0 0 pcep gipsp write reset 000000000000 0000
register descriptions 56f8023 data sheet, rev. 3 freescale semiconductor 91 preliminary figure 6-18 overall control of signal source using sim_gps nn control in some cases, the user can choose peripheral functi on between several i/o, each of which have the option to be programmed to control a specific peripheral func tion. if the user wishes to use that function, only one of these i/o must be configured to control that peripheral function. if more than one i/o is configured to control the peripheral function, the pe ripheral output signal will fan out to each i/o, but the peripheral input signal will be the logical or and and of all the i/o signals. complete lists of i/o muxings are provided in table 2-3 . the gps n setting can be altered during no rmal operation, but a delay must be inserted between the time when one function is disabled and another function is enabled. note: after reset, all i/o pins are gpio, except the jtag pins and the reset pin. figure 6-19 gpio peripheral select register 0 for gpioa (sim_gpsa0) 6.3.16.1 reserved?bits 15?13 this bit field is reserved. each bit must be set to 0. 6.3.16.2 configure gpioa6 (gps_a6)?bit 12 this field selects the alte rnate function for gpioa6. ? 0 = fault0 - pwm fault0 input (default) ? 1 = ta0 - timer a0 base + $13 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 gps_a6 gps_a5 gps_a4 0 0 0 0 0 0 0 0 write reset 000 0 00000000 0000 gpioa6_peren register gpioa6 gpioa6 pin sim_gpsa0 register pwm fault0 timer a0 0 1 0 1
56f8023 data sheet, rev. 3 92 freescale semiconductor preliminary 6.3.16.3 configure gpioa5 (gps_a5)?bits 11?10 this field selects the alte rnate function for gpioa5. ? 00 = pwm5 - pwm5 (default) ? 01 = fault2 - pwm fault2 input ? 10 = ta3 - timer a3 ?11 = reserved 6.3.16.4 configure gpioa4 (gps_a4)?bits 9?8 this field selects the alte rnate function for gpioa4. ? 00 = pwm4 - pwm4 (default) ? 01 = fault1 - pwm fault1 input ? 10 = ta2 - timer a2 ?11 = reserved 6.3.16.5 reserved?bits 7?0 this bit field is reserved. each bit must be set to 0. 6.3.17 sim gpio peripheral select register 0 for gpiob (sim_gpsb0) see section 6.3.16 for general information about gp io peripheral select registers. figure 6-20 gpio peripheral select register 0 for gpiob (sim_gpsb0) 6.3.17.1 reserved?bit 15 this bit field is reserved. it must be set to 0. 6.3.17.2 configure gpiob6 (gps_b6)?bits 14?13 this field selects the alte rnate function for gpiob6. ? 00 = rxd0 - qsci0 receive data (default) ? 01 = sda - i2c serial ? 10 = clkin - external clock input ?11 = reserved base + $15 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 gps_b6 gps_b5 gps_b4 gps_b3 gps_b2 0 gps_ b1 0 gps_ b0 write reset 000000000000 0000
register descriptions 56f8023 data sheet, rev. 3 freescale semiconductor 93 preliminary 6.3.17.3 configure gpiob5 (gps_b5)?bits 12?11 this field selects the alte rnate function for gpiob5. ? 00 = ta1 - timer a1 (default) ? 01 = fault3 - pwm fault3 input ? 10 = clkin - external clock input ?11 = reserved 6.3.17.4 configure gpiob4 (gps_b4)?bits 10?8 this field selects the alte rnate function for gpiob4. ? 000 = ta0 - timer a0 (default) ? 001 = clko - clock output ? 010 = reserved ? 011 = tb0 - timer b0 ? 100 = psrc2 - pwm4 / pwm5 pair external source ? 11x = reserved ? 1x1 = reserved 6.3.17.5 configure gpiob3 (gps_b3)?bits 7?6 this field selects the alte rnate function for gpiob3. ? 00 = mosi0 - qspi0 master out/slave in (default) ? 01 = ta3 - timer a3 ? 10 = psrc1 - pwm2 / pwm3 pair external source ?11 = reserved 6.3.17.6 configure gpiob2 (gps_b2)?bits 5?4 this field selects the alte rnate function for gpiob2. ? 00 = miso0 qspi0 master in/slave out (default) ? 01 = ta2 - timer a2 ? 10 = psrc0 - pwm0 / pwm1 pair external source ?11 = reserved 6.3.17.7 reserved?bit 3 this bit field is reserved. it must be set to 0. 6.3.17.8 configure gpiob1 (gps_b1)?bit 2 this field selects the alte rnate function for gpiob1. ?0 = ss 0 - qspi0 slave select (default) ? 1 = sda - i2c serial data
56f8023 data sheet, rev. 3 94 freescale semiconductor preliminary 6.3.17.9 reserved?bit 1 this bit field is reserved. it must be set to 0. 6.3.17.10 configure gp iob0 (gps_b0)?bits 0 this field selects the alte rnate function for gpiob0. ? 0 = sclk0 - qspi0 serial clock (default) ? 1 = scl - i 2 c serial clock 6.3.18 sim gpio peripheral select register 1 for gpiob (sim_gpsb1) see section 6.3.16 for general information about gp io peripheral select registers. figure 6-21 gpio peripheral select register 1 for gpiob (sim_gpsb1) 6.3.18.1 reserved?bits 15?1 this bit field is reserved. each bit must be set to 0. 6.3.18.2 configure gpiob7 (gps_b7)?bit 0 this field selects the alte rnate function for gpiob7. ? 0 = txd0 - qsci0 transmit data (default) ? 1 = scl - i 2 c serial clock 6.3.19 internal peripheral source select register 0 for pulse width modulator (sim_ips0) the internal integration of periphera ls provides input signal source selection for pe ripherals where an input signal to a peripheral can be fed fr om one of several sources. these registers are organized by peripheral type and provide a selection list fo r every peripheral input signal that ha s more than one alternative source to indicate which source is selected. if one of the alternative s ources is gpio, the setting in these registers must be ma de consistently with the settings in the gps n and gpio x _peren registers. specifically, when an ips n field is configured to select an i/o pin as the source, then gps n register settings must configure onl y one i/o pin to fe ed this peripheral input function. also, the gpio x _peren bit for that i/o pi n must be set to 1 to enable peripheral control of the i/o. base + $16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 gps_ b7 write reset 000000000000 0000
register descriptions 56f8023 data sheet, rev. 3 freescale semiconductor 95 preliminary figure 6-22 overall control of signal source using sim_ips n control ips n settings should not be altere d while an affected peripheral is in an enabled (operational) configuration. see the 56f802x and 56f803x peripheral reference manual for details. figure 6-23 internal peripheral source select register for pwm (sim_ips0) 6.3.19.1 reserved?bits 15?14 this bit field is reserved. each bit must be set to 0. 6.3.19.2 select peripheral input so urce for fault2 (ips0_fault2)?bit 13 this field selects the alte rnate input source signal to feed pwm input fault2. ? 0 = i/o pin (external) - use pwm fault2 input pin (default) ? 1 = cmpbo (internal) - use comparator b output 6.3.19.3 reserved?bit 12 this bit field is reserved. it must be set to 0. 6.3.19.4 select peripheral input so urce for fault1 (ips0_fault1)?bit 11 this field selects the alte rnate input source signal to feed pwm input fault1. ? 0 = i/o pin (external) - use pwm fault2 input pin (default) ? 1 = cmpao (internal) - use comparator a output base + $18 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 ips0_ fault2 0 ips0_ fault1 0 0 ips0_psrc2 ips0_psrc1 ips0_psrc0 write reset 00 0 0 0 0000000 0000 gpioa5_peren register gpioa5 gpioa5 pin sim_ips0 register pwm fault2 comparator a output (internal) 0 1 0 1 01 00 10 pwm5 timer a3 sim_gpsa0 register
56f8023 data sheet, rev. 3 96 freescale semiconductor preliminary 6.3.19.5 reserved?bits 10?9 this bit field is reserved. each bit must be set to 0. 6.3.19.6 select peripheral input source for pwm4/pwm5 pair source (ips0_psrc2)?bits 8?6 this field selects the alternate input source signa l to feed pwm input psrc 2 as the pwm4/pwm5 pair source. ? 000 = reserved (default) ? 001 = ta3 (internal) - use ti mer a3 output as pwm source ? 010 = adc sample2 (internal) - use adc sample2 result as pwm source ? if the adc conversion result in sample2 is greater than the value programm ed into the high limit register hlmt2, then pwm4 is set to 0 and pwm5 is set to 1 ? if the adc conversion result in sample2 is less than the value programm ed into the low limit register llmt2, then pwm4 is set to 1 and pwm5 is set to 0 ? 011 = cmpao (internal) - use comparator a output as pwm source ? 100 = cmpbo (internal) - use co mparator b output as pwm source ? 11x = reserved ? 1x1 = reserved 6.3.19.7 select peripheral input source for pwm2/pwm3 pair source (ips0_psrc1)?bits 5?3 this field selects the alternate input source signa l to feed pwm input psrc 1 as the pwm2/pwm3 pair source. ? 000 = i/o pin (external) - use a psrc1 input pin as pwm source (default) ? 001 = ta2 (internal) - use ti mer a2 output as pwm source ? 010 = adc sample1 (internal) - use adc sample1 result as pwm source ? if the adc conversion result in sample1 is greater than the value programm ed into the high limit register hlmt1, then pwm2 is set to 0 and pwm3 is set to 1 ? if the adc conversion result in sample1 is less than the value programm ed into the low limit register llmt2, then pwm2 is set to 1 and pwm3 is set to 0 ? 011 = cmpao (internal) - use comparator a output as pwm source ? 100 = cmpbo (internal) - use comparator b output as pwm source ? 11x = reserved ? 1x1 = reserved
register descriptions 56f8023 data sheet, rev. 3 freescale semiconductor 97 preliminary 6.3.19.8 select peripheral input source for pwm0/pwm1 pair source (ips0_psrc0)?bits 2?0 this field selects the alternate input source signa l to feed pwm input psrc 0 as the pwm0/pwm1 pair source. ? 000 = i/o pin (external) - use a psrc0 input pin as pwm source (default) ? 001 = ta0 (internal) - use ti mer a0 output as pwm source ? 010 = adc sample0 (internal) - use adc sample0 result as pwm source ? if the adc conversion result in sample0 is greater than the value programm ed into the high limit register hlmt1, then pwm0 is set to 0 and pwm1 is set to 1 ? if the adc conversion result in sample0 is less than the value programm ed into the low limit register llmt2, then pwm0 is set to 1 and pwm1 is set to 0 ? 011 = cmpao (internal) - use comparator a output as pwm source ? 100 = cmpbo (internal) - use comparator b output as pwm source ? 11x = reserved ? 1x1 = reserved 6.3.20 internal peripheral source se lect register 1 for digital-to-analog converters (sim_ips1) see section 6.3.19 for general information about internal peripheral source select registers. figure 6-24 internal peri pheral source select regi ster for dacs (sim_ips1) 6.3.20.1 reserved?bits 15?7 this bit field is reserved. each bit must be set to 0. 6.3.20.2 select peripheral inpu t source for sync input to dac 1 (iss1_dsync1)-bits 6-4 this field selects the a lternate input source signal to feed dac1 sync input. ? 000 = pit0 (internal) ? use programmable interv al timer 0 output as dac sync input (default) ? 001 = reserved ? 010 = reserved ? 011 = pwm sync (internal) - use pwm reload synchronization signal as dac sync input ? 100 = ta0 (internal) - use time r a0 output as dac sync input ? 101 = ta1 (internal) - use time r a1 output as dac sync input ? 11x = reserved base + $19 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 0 0 ips1_dsync1 0 ips1_dsync0 write reset 000000000000 0000
56f8023 data sheet, rev. 3 98 freescale semiconductor preliminary 6.3.20.3 select peripheral inpu t source for sync input to dac 0 (iss1_dsync0)?bits 2?0 this field selects the a lternate input source signal to feed dac0 sync input. ? 000 = pit0 (internal) - use programmable interv al timer 0 output as dac sync input (default) ? 001 = reserved ? 010 = reserved ? 011 = pwm sync (internal) - use pwm reload synchronization signal as dac sync input ? 100 = ta0 (internal) - use time r a0 output as dac sync input ? 101 = ta1 (internal) - use time r a1 output as dac sync input ? 11x = reserved 6.3.21 internal peripheral source select register 2 for quad timer a (sim_ips2) see section 6.3.19 for general information about internal peripheral source select registers. figure 6-25 internal peripheral source select register for tmra (sim_ips2) 6.3.21.1 reserved?bits 15?13 this bit field is reserved. each bit must be set to 0. 6.3.21.2 select peripheral inpu t source for ta3 (ips2_ta3)?bit 12 this field selects the altern ate input source signal to feed quad timer a, input 3. ? 0 = i/o pin (external) - use timer a3 input/output pin ? 1 = pwm sync (internal) - use pwm reload synchronization signal 6.3.21.3 reserved?bits 11?9 this bit field is reserved. each bit must be set to 0. 6.3.21.4 select input sour ce for ta2 (iss2_ta2)?bit 8 this field selects the altern ate input source signal to feed quad timer a, input 2. ? 0 = i/o pin (external) - use timer a2 input/output pin ? 1 = cmpbo (internal) - use comparator b output base + $1a 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 ips2_ ta3 0 0 0 ips2_ ta2 0 0 0 ips2_ ta1 0 0 0 0 write reset 000000000000 0000
clock generation overview 56f8023 data sheet, rev. 3 freescale semiconductor 99 preliminary 6.3.21.5 reserved?bits 7?5 this bit field is reserved. each bit must be set to 0. 6.3.21.6 select peripheral inpu t source for ta1 (ips2_ta1)?bit 4 this field selects the altern ate input source signal to feed quad timer a, input 1. ? 0 = i/o pin (external) - use timer a1 input/output pin ? 1 = cmpao (internal) - use comparator a output 6.3.21.7 reserved?bits 3?0 this bit field is reserved. each bit must be set to 0. for timer a to detect the pwm sync signal, th e clock rate of both the pwm module and timer a module must be identical, at either the syst em clock rate or 3x system clock rate. 6.4 clock generation overview the sim uses the master clock (2x system clock) at a maximum of 64mhz from the occs module to produce a system clock at a maximu m of 32mhz for the peripheral, co re, and memory. it divides the master clock by two and gates it with appropriate power mode and clock gating controls. a 3x system high-speed peripheral clock input from occs operates at three tim es the system clock at a maximum of 96mhz and can be an optional cl ock for pwm, timer a, and i 2 c modules. these clocks are generated by gating the 3x system high-speed pe ripheral clock with appropriate power mode and clock gating controls. the occs configuration controls the operating frequenc y of the sim?s master cl ocks. in the occs, either an external clock (clkin), a crysta l oscillator, or the rela xation oscillator can be selected as the master clock source (mstr_osc). an extern al clock can be operate d at any frequency up to 64mhz. the crystal oscillator can be operated only at a maximum of 8mhz. the relaxation oscillator can be operated at full speed (8mhz), standby speed (4 00khz using rosb), or powered down (using ropd). an 8mhz mstr_osc can be multiplied to 19 6mhz using the pll and postscaled to provide a variety of high-speed clock rates. either the postscaled pll output or mstr_osc signal can be selected to produce the master clocks to the sim. when the pll is selected, both the 3x system cl ock and the 2x system clock are enabled. if the pll is not selecte d, the 3x system clock is disabled and the master clock is mstr_osc. in combination with the occs modul e, the sim provides power modes (see section 6.5 ), clock enables, and clock rate controls to provide flexible control of clocking and power utilizat ion. the clock rate controls enable the high-speed clocking option for the two quad timers (tmra and tmrb) and pwm, but requires the pll to be on and selected. refer to the 56f802x and 56f803x p eripheral reference manual for further details. the peripheral clock enable controls can be used to disable an individual peripheral clock when it is not used.
56f8023 data sheet, rev. 3 100 freescale semiconductor preliminary 6.5 power-saving modes the 56f8023 operates in one of five power-saving modes, as shown in table 6-2 . the power-saving modes provide additional power management opt ions by disabl ing the clock, reconfiguring the voltage regulat or clock generation to manage power utilization, as shown in table 6-2 . run, wait, and stop modes provide me thods of enabling/disabling the pe ripheral and/or core clocking as a group. stop disable contro ls for an individual periphe ral are provided in the sd n registers to override the default behavior of stop m ode. by asserting a peripher al?s stop disable bit, the peripheral clock continues table 6-2 clock operati on in power-saving modes mode core clocks peripheral clocks description run core and memory clocks enabled peripheral clocks enabled device is fully functional wait core and memory clocks disabled peripheral clocks enabled core executes wait instruction to enter this mode. typically used for power-conscious applications. possible recoveries from wait mode to run mode are: 1. any interrupt 2. executing a debug mode entry command during the 56800e core jtag interface 3. any reset (por, external, software, cop) stop master clock generation in the occs remains operational, but the sim disables the generation of system and peripheral clocks. core executes stop instruction to enter this mode. possible recoveries from stop mode to run mode are: 1. interrupt from any peripheral configured in the ctrl register to operate in stop mode (ta0-3, qsci0, pit0-1, can, cmpa-b) 2. low-voltage interrupt 3. executing a debug mode entry command using the 56800e core jtag interface 4. any reset (por, external, software, cop) standby the occs generates the master clock at a reduced frequency (400khz). the pll is disabled and the high-speed peripheral option is not available. system and peripheral clocks operate at 200khz. the user configures the occs and sim to select the relaxation oscillator clock source (precs), shut down the pll (pllpd), put the relaxation oscillator in standby mode (rosb), and put the large regulator in standby (lrstdby). the device is fully operational, but operating at a minimum frequency and power configuration. recovery requires reversing the sequence used to enter this mode (a llowing for pll lock time). power-down master clock generation in the occs is completely shut down. all system and peripheral clocks are disabled. the user configures the occs and sim to enter standby mode as shown in the previous description, followed by powering down the oscillator (ropd). the only possible recoveries from this mode are: 1. external reset 2. power-on reset
resets 56f8023 data sheet, rev. 3 freescale semiconductor 101 preliminary to operate in stop mode. this is useful to generate interrupts which will recove r the device from stop mode to run mode. standby mode provides normal operation but at very low speed and pow er utilization. it is possible to invoke stop or wait mode while in standby mode for even greater le vels of power reduction. a 400khz external clock can optiona lly be used in standby mode to produce the required standby 200khz system clock rate. power-down mode, which selects the rosc clock source but shuts it off, fully disables the device and minimizes its power utilization but is only recoverable via reset. when the pll is not selected and the system bus is operating at 200khz or less, the large regulator can be put into its standby mode (lrstdby) to redu ce the power utilizati on of that regulator. all peripherals, except the cop/watc hdog timer, run at the system cloc k frequency or optional 3x system clock for pwm, timers, and i 2 c. the cop timer runs at osc_ clk / 1024. the maxi mum frequency of operation is 32mhz. 6.6 resets the sim supports five sources of reset, as shown in figure 6-26 . the two asynchronous sources are the external reset pin and the power-on reset (por). th e three synchronous sources are the software reset (sw reset), which is generated within the sim itself by writing the si m_ctrl register in section 6.3.1 , the cop time-out reset (cop_tor), and the co p loss-of-reference reset (cop_lor). the reset generation module has three reset dete ctors, which resolve into four pr imary resets. these are outlined in table 6-3 . the jtag circuitry is reset by the power-on reset. figure 6-26 provides a graphic illustration of the details in table 6-3 . note that the por_delay blocks use the osc_clk as their time base , since other system cl ocks are inactive during this phase of reset. table 6-3 primary system resets reset sources reset signal por external software cop comments extended_por x stretched version of por released 64 osc_clk cycles after por deasserts clkgen_rst xxxxreleased 32 osc_clk cycles after all reset sources, including extended_por , have released perip_rst xxxxreleases 32 sys_clk cycles after the clkgen_rst is released core_rst xxxxreleases 32 sys_clk cycles after perip_rst is released
56f8023 data sheet, rev. 3 102 freescale semiconductor preliminary figure 6-26 sources of r eset functional diagram (t est modes not included) por resets are extended 64 osc_cl k clocks to stabilize the power supply and clock source. all resets are subsequently extended for an additional 32 osc_clk clocks and 64 system cloc ks as the various internal reset controls are release d. given the normal relaxa tion oscillator rate of 8mhz, the duration of a por reset from when power comes on to when code is running is 28 s. an external reset generation circuit may also be used. a description of how these resets are us ed to initialize the clocking system and system modules is included in section 6.7 . 6.7 clocks the memory, peripheral and core clocks all operate at the same frequency ( 32mhz maximum), with the exception of the peripheral clocks for quad timers tmra and tmrb and the pwm, which have the option to operate at 3x system clock. the sim is responsible for clock distributions. while the sim generates the adc peripheral clock in th e same way it generates al l other peripheral clocks, the adc standby and conversion cloc ks are generated by a direct in terface between the adc and the occs module. extended_por jtag memory subsystem peripherals 56800e core_rst delay 32 sys clocks occs clkgen_rst perip_rst delay 32 sys clocks pulse shaper pulse shaper sw reset pulse shaper delay 32 osc_clk clock pulse shaper por power-on reset (active low) external reset in (active low) reset delay 64 osc_clk clock delay blocks asse rt immediately and deassert only after the programmed number of clock cycles. combined_rst cop_lor (active low) cop_tor (active low)
clocks 56f8023 data sheet, rev. 3 freescale semiconductor 103 preliminary the deassertion sequence of internal resets coordi nates the device start up, including the clocking system start up. the sequence is descri bed in the following steps: 1. as power is applied, the relaxa tion oscillator starts to operate. when a valid operating voltage is reached, the por reset will release. 2. the release of por reset permits operation of th e por reset extender. the por extender generates an extended por reset, which is released 64 os c_clk cycles after por reset. this provides an additional time period for the cloc k source and power to stabilize. 3. a combined reset consists of the or of the exte nded por reset, the external reset, the cop reset and software reset. the entire device, except for the por extender, is he ld reset as long as combined reset is asserted. the release of combin ed reset permits operation of the ctrl register, the synchronous reset generator, and the clkgen reset extender. 4. the synchronous reset generator generates a reset to the software and cop reset logic. the cop and software reset logic is released three osc_clk cycles after combined reset deasserts. this provides a reasonable minimum duration to the reset for these specialized functions. 5. the clkgen reset extender generates the clkgen reset used by the clock generation logic. the clkgen reset is released 32 osc_clk cycles af ter combined reset deasserts. this provides a window in which the sim stab ilizes the master clock inpu ts to the clock generator. 6. the release of clkgen reset permits operation of the clock generation logic and the peripheral reset extender. the peripheral reset extender genera tes the peripheral reset, which is released 32 sys_clk cycles after clkgen reset. this provides a window in which peripheral and core logic remain clocked, but in re set, so that synchronous resets can be resolved. 7. the release of peripheral reset permits operation of the peripheral logic and the core reset extender. the core reset extender generat es the core reset, which is released 32 sys_clk cycles after the peripheral reset. this provides a window in whic h critical peripheral start-up functions, such as flash security in the flash memory, can be implemented. 8. the release of core reset permits execution of c ode by the 56800e core and marks the end of the system start-up sequence. figure 6-27 illustrates clock relationships to one another and to the various resets as the device comes out of reset. rst is assumed to be the logical and of all active-low system rese ts (for example, por, external reset, cop and software reset). in the 56f8023, this signal will be stretched by the sim for a period of time (up to 96 osc_clk clock cycles, depending upon the status of the por) to create the clock generation reset signal (clkgen_rst ). the sim should deassert clkgen_rst synchronously with the negative edge of osc_clk in orde r to avoid skew problems. clkgen_rst is delayed 32 sys_clk cycles to create the peri pheral reset signal (perip_rst ). perip_rst is then delayed by 32 sys_clk cycles to create core_rst . both perip_rst and core_rst should be released on the negative edge of sys_clk_d as shown. this phased releasing of sy stem resets is necessary to give some peripherals (for example, the flash interface unit) set-up time prior to the 56800e core becoming active.
56f8023 data sheet, rev. 3 104 freescale semiconductor preliminary figure 6-27 timing relationships of reset signal to clocks 6.8 interrupts the sim generates no interrupts. part 7 security features the 56f8023 offers security features intended to prevent unauthoriz ed users from reading the contents of the flash memory (fm) array. the 56f 8023?s flash security c onsists of several hardware interlocks that prevent unauthorized users from ga ining access to the flash array. note, however, that part of the security must lie with the user?s code. an extreme exam ple would be user?s code that includes a subroutin e to read and transfer the contents of the internal program to qsci, qspi or another peripheral, as this code would defeat the pur pose of security. at the sa me time, the user may also wish to put a ?backdoor? in his progr am. as an example, the user dow nloads a security key through the qsci, allowing access to a pr ogramming routine that updates parameters stored in another section of the flash. 7.1 operation with security enabled once the user has programmed the flash with his application c ode, the 56f8023 can be secured by programming the security bytes locate d in the fm configurat ion field, which are lo cated at the last nine words of program flash. these non-vol atile bytes will keep the device secured through reset and through rst mstr_osc ckgen_rst 2x sys_clk sys_clk sys_clk_d sys_clk_div2 perip_rst core_rst switch on falling osc_clk 96 mstr_osc cycles switch on falling sys_clk 32 sys_clk cycles delay 32 sys_clk cycles delay maximum delay = 64 osc_clk cycles for por reset extension and 32 osc_clk cycles for combined reset extension switch on falling sys_clk
flash access lock and unlock mechanisms 56f8023 data sheet, rev. 3 freescale semiconductor 105 preliminary power-down of the device. only two byt es within this field are used to enable or disable security. refer to the flash memory chapter in the 56f802x and 56f803x peripheral reference manual for the state of the security bytes and the resulting state of security. when flash securi ty mode is enabled in accordance with the method described in the fl ash memory module chapter, the 56f8023 will disable the core eonce debug capabilities. normal program execution is otherwise unaffected. 7.2 flash access lock and unlock mechanisms the 56f8023 has several operating f unctional and debug modes. effectiv e flash security must address operating mode selection and anticipa te modes in which the on-chip flas h can be read wi thout explicit user permission. 7.2.1 disabling eonce access on-chip flash can be read by issui ng commands across the eonce port, which is the debug interface for the 56800e cpu. the tck, tms, td o, and tdi pins comprise a jtag interface onto which the eonce port functionality is mapped. when the 56f8023 boots, the chip-l evel jtag tap (test access port) is active and provides the chip?s boun dary scan capability and access to the id register, but proper implementation of flash s ecurity will block any a ttempt to access the internal flash memory via the eonce port when security is enabled. 7.2.2 flash lockout recovery using jtag if a user inadvertently enables security on th e 56f8023, the only lockout reco very mechanism is the complete erasure of the internal flash contents, incl uding the configuration field, and thus disables security (the protection register is cleared). this does not compromise security, as the entire contents of the user?s secured code stored in flash are erased before security is disabled on the 56f8023 on the next reset or power-up sequence. to start the lockout recovery sequence, the jtag public inst ruction (lockout_recovery) must first be shifted into the chip-level tap c ontroller?s instruction register. once the lockout_recovery instruction has be en shifted into the instruction register, the clock divider value must be shifted into the co rresponding 7-bit data register. after the da ta register has been updated, the user must transition the tap c ontroller into the run-test/ idle state for the lockout sequence to commence. the controller must remain in this state until the erase seque nce has completed. refer to the 56f802x and 56f803x peripheral reference manual for more details, or contact freescale. note: once the lockout recovery sequence has completed, the user must reset both the jtag tap controller (by advancing the tap state machine to the reset st ate) and the 56f8023 (by asserting external chip reset) to return to no rmal unsecured operation. 7.2.3 flash lockout recovery using codewarrior codewarrior can unlock a device usi ng the command sequence described in section 7.2.2 by selecting the debug menu, then selecting dsp56800e , followed by unlock flash .
56f8023 data sheet, rev. 3 106 freescale semiconductor preliminary another mechanism is also built in to codewarrior using the device?s memory configuration file. the command ? unlock_flash_on_connect1 ? in the . cfg file accomplishes the same task as using the debug menu. 7.2.4 product analysis the recommended method of unsecuri ng a programmed 56f8023 for product an alysis of field failures is via the backdoor key access. the customer would need to s upply technical support with the backdoor key and the protocol to acce ss the backdoor routine in the flash. a dditionally, the keyen bit that allows backdoor key access must be set. an alternative method for performing analysis on a s ecured microcontroller woul d be to mass-erase and reprogram the flash with the original code, but modify the security bytes. to insure that a customer does not inadvertently lock himself out of the 56f8023 during programming, it is recommended that the user program the backdoor access key first, the applic ation code second, and the security bytes within the fm configuration field last. part 8 general-purpose input/output (gpio) 8.1 introduction this section is intended to suppleme nt the gpio information found in the 56f802x and 56f803x peripheral reference manual and contains only chip-s pecific information. this information supersedes the generic information in the 56f802x and 56f803x peripheral reference manual . 8.2 configuration there are four gpio ports define d on the 56f8023. the width of each por t, the associated peripheral and reset functions are shown in table 8-1 . the specific mapping of gpio port pins is shown in table 8-2 . additional details are shown in tables 2-2 and 2-3 . table 8-1 gpio ports configuration gpio port available pins in 56f8023 peripheral function reset function a8 pwm, timer, qspi, comp arator, reset gpio, reset b8 qspi, i 2 c, pwm, clock, comparator, timer gpio c6 adc, comparator, qsci gpio d4 clock, oscillator, jtag gpio, jtag
configuration 56f8023 data sheet, rev. 3 freescale semiconductor 107 preliminary table 8-2 gpio external signals map gpio function peripheral function lqfp package pin notes gpioa0 pwm0 29 defaults to a0 gpioa1 pwm1 28 defaults to a1 gpioa2 pwm2 23 defaults to a2 gpioa3 pwm3 24 defaults to a3 gpioa4 pwm4 / ta2 / fault1 22 sim register sim_gps is used to select between pwm4, ta2, and fault1. defaults to a4 gpioa5 pwm5 / ta3 / fault2 20 sim register sim_gps is used to select between pwm5, ta3, and fault2. defaults to a5 gpioa6 fault0 / ta0 18 sim register sim_gps is used to select between fault0 and ta0. defaults to a6 gpioa7 reset 15 defaults to reset gpiob0 sclk0 / scl 21 sim register sim_gps is used to select between sclk and scl. defaults to b0 gpiob1 ss 0 / sda 2 sim register sim_gps is used to select between ss 0 and sda. defaults to b1 gpiob2 miso0 / ta2 / psrc0 17 sim register sim_gps is used to select between miso0, ta2, and psrc0. defaults to b2 gpiob3 mosi0 / ta3 / psrc1 16 sim register sim_gps is used to select between mosi0, ta3 and psrc1. defaults to b3 gpiob4 ta0 / clko / psrc2 38 sim r egister sim_gps is used to select between ta0, clko, and psrc2. defaults to b4
56f8023 data sheet, rev. 3 108 freescale semiconductor preliminary 8.3 reset values tables 8-1 and 8-2 detail registers fo r the 56f8023; figures 8-1 through 8-4 summarize register maps and reset values. gpiob5 ta1 / fault3 / clkin 4 sim register sim_gps is used to select between ta1, fault3, and clkin. clkin functionality is enabled using the pll control register within the occs block. defaults to b5 gpiob6 rxd0 / sda / clkin 1 sim r egister sim_gps is used to select between rxd0, sda, and clkin. clkin functionality is enabled using the pll control register within the occs block. defaults to b6 gpiob7 txd0 / scl 3 sim regist er sim_gps is used to select between txd0 and scl. defaults to b7 gpioc0 ana0 & cmpai3 12 defaults to c0 gpioc1 ana1 11 defaults to c1 gpioc2 ana2 / v refha 10 sim register sim_gps is used to select between ana2 and v refha . defaults to c2 gpioc4 anb0 / cmpbi3 5 sim regi ster sim_gps is used to select between anb0 and cmpbi3. defaults to c4 gpioc5 anb1 6 defaults to c5 gpioc6 anb2 / v refhb 7 sim register sim_gps is used to select between anb2 and v refhb . defaults to c6 gpiod0 tdi 30 defaults to tdi gpiod1 tdo 32 defaults to tdo gpiod2 tck 14 defaults to tck gpiod3 tms 31 defaults to tms table 8-2 gpio external signals map (continued) gpio function peripheral function lqfp package pin notes
reset values 56f8023 data sheet, rev. 3 freescale semiconductor 109 preliminary figure 8-1 gpioa register map summary add. offset register acronym 151413121110987654321 0 $0 gpioa_pupen r pu[15:0] w rs 0 1 1 1 1 1 1 1 11111111 $1 gpioa_data r d[15:0] w rs 0 0 0 0 0 0 0 0 00000000 $2 gpioa_ddir r dd[15:0] w rs 0 0 0 0 0 0 0 0 00000000 $3 gpioa_peren r pe[15:0] w rs 0 0 0 0 0 0 0 0 00000000 $4 gpioa_iassrt r ia[15:0] w rs 0 0 0 0 0 0 0 0 00000000 $5 gpioa_ien r ien[15:0] w rs 0 0 0 0 0 0 0 0 00000000 $6 gpioa_iepol r iepol[15:0] w rs 0 0 0 0 0 0 0 0 00000000 $7 gpioa_ipend r ipr[15:0] w rs 0 0 0 0 0 0 0 0 00000000 $8 gpioa_iedge r ies[15:0] w rs 0 0 0 0 0 0 0 0 00000000 $9 gpioa_ppoutm r oen[15:0] w rs 0 1 1 1 1 1 1 1 11111111 $a gpioa_rdata r raw data[15:0] w rs 0 x x x x x x x xxxxxxxx $b gpioa_drive r drive[15:0] w rs 0 0 0 0 0 0 0 0 00000000 r 0 read as 0 w reserved rs reset
56f8023 data sheet, rev. 3 110 freescale semiconductor preliminary figure 8-2 gpiob register map summary add. offset register acronym 151413121110987654321 0 $0 gpiob_pupen r pu[15:0] w rs 0 1 1 1 1 1 1 1 11111111 $1 gpiob_data r d[15:0] w rs 0 0 0 0 0 0 0 0 00000000 $2 gpiob_ddir r dd[15:0] w rs 0 0 0 0 0 0 0 0 00000000 $3 gpiob_peren r pe[15:0] w rs 0 0 0 0 0 0 0 0 00000000 $4 gpiob_iassrt r ia[15:0] w rs 0 0 0 0 0 0 0 0 00000000 $5 gpiob_ien r ien[15:0] w rs 0 0 0 0 0 0 0 0 00000000 $6 gpiob_iepol r iepol[15:0] w rs 0 0 0 0 0 0 0 0 00000000 $7 gpiob_ipend r ipr[15:0] w rs 0 0 0 0 0 0 0 0 00000000 $8 gpiob_iedge r ies[15:0] w rs 0 0 0 0 0 0 0 0 00000000 $9 gpiob_ppoutm r oen[15:0] w rs 0 1 1 1 1 1 1 1 11111111 $a gpiob_rdata r 0 0 raw data[15:0] w rs 0 0 x x x x x x xxxxxxxx $b gpiob_drive r drive[15:0] w rs 0 0 0 0 0 0 0 0 00000000 r 0 read as 0 w reserved rs reset
reset values 56f8023 data sheet, rev. 3 freescale semiconductor 111 preliminary figure 8-3 gpioc register map summary add. offset register acronym 151413121110987654321 0 $0 gpioc_pupen r pu[15:0] pu w rs 1 1 1 1 1 1 1 1 1 111 1 111 $1 gpioc_data r d[15:0] d w rs 0 0 0 0 0 0 0 0 0 000 0 000 $2 gpioc_ddir r dd[15:0] dd w rs 0 0 0 0 0 0 0 0 0 000 0 000 $3 gpioc_peren r pe[15:0] pe w rs 0 0 0 0 0 0 0 0 0 000 0 000 $4 gpioc_iassrt r ia[15:0] ia w rs 0 0 0 0 0 0 0 0 0 000 0 000 $5 gpioc_ien r ien[15:0] ien w rs 0 0 0 0 0 0 0 0 0 000 0 000 $6 gpioc_iepol r iepol[15:0] iepol w rs 0 0 0 0 0 0 0 0 0 000 0 000 $7 gpioc_ipend r ipr[15:0] ipr w rs 0 0 0 0 0 0 0 0 0 000 0 000 $8 gpioc_iedge r ies[15:0] ies w rs 0 0 0 0 0 0 0 0 0 000 0 000 $9 gpioc_ppoutm r oen[15:0] oen w rs 1 1 1 1 1 1 1 1 1 111 1 111 $a gpioc_rdata r raw data[15:0] raw data w rs x x x x x x x x x xxx x xxx $b gpioc_drive r drive[15:0] drive w rs 0 0 0 0 0 0 0 0 0 000 0 000 r 0 read as 0 w reserved rs reset
56f8023 data sheet, rev. 3 112 freescale semiconductor preliminary figure 8-4 gpiod register map summary add. offset register acronym 151413121110987654321 0 $0 gpiod_pupen r pu[15:0] w rs 0 0 0 0 0 0 0 0 1 1 1 1 1111 $1 gpiod_data r d[15:0] w rs 0 0 0 0 0 0 0 0 0 0 0 0 0000 $2 gpiod_ddir r dd[15:0] w rs 0 0 0 0 0 0 0 0 0 0 0 0 0000 $3 gpiod_peren r pe[15:0] w rs 0 0 0 0 0 0 0 0 0 0 0 0 1111 $4 gpiod_iassrt r ia[15:0] w rs 0 0 0 0 0 0 0 0 0 0 0 0 0000 $5 gpiod_ien r ien[15:0] w rs 0 0 0 0 0 0 0 0 0 0 0 0 0000 $6 gpiod_iepol r iepol[15:0] w rs 0 0 0 0 0 0 0 0 0 0 0 0 0000 $7 gpiod_ipend r ipr[15:0] w rs 0 0 0 0 0 0 0 0 0 0 0 0 0000 $8 gpiod_iedge r ies[15:0] w rs 0 0 0 0 0 0 0 0 0 0 0 0 0000 $9 gpiod_ppoutm r oen[15:0] w rs 0 0 0 0 0 0 0 0 1 1 1 1 1111 $a gpiod_rdata r raw data[15:0] w rs 0 0 0 0 0 0 0 0 x x x x xxxx $b gpiod_drive r drive[15:0] w rs 0 0 0 0 0 0 0 0 0 0 0 0 0000 r 0 read as 0 w reserved rs reset
56f8023 information 56f8023 data sheet, rev. 3 freescale semiconductor 113 preliminary part 9 joint test action group (jtag) 9.1 56f8023 information please contact your freescale sales representative or authorized distributor fo r device/package-specific bsdl information. the trst pin is not available in this package. the pin is tied to v dd in the package. the jtag state machine is reset during por and can also be reset via a soft reset by holding tms high for five rising edges of tc k, as described in the 56f802x and 56f803x peri pheral reference manual . part 10 specifications 10.1 general characteristics the 56f8023 is fabricated in high-de nsity cmos with 5v-tolerant ttl- compatible digital inputs. the term ?5v-tolerant? refers to the capability of an i/o pin, built on a 3.3v-c ompatible process technology, to withstand a voltage up to 5.5v without damaging the devi ce. many systems have a mixture of devices designed for 3.3v and 5v pow er supplies. in such systems, a bus may carry both 3.3v- and 5v-compatible i/o voltage levels (a standard 3.3v i/o is designed to rece ive a maximum voltage of 3.3v 10% during normal operation without causing damage ). this 5v-tolerant capability therefore offers the power savings of 3.3v i/o levels, combined with the abi lity to receive 5v le vels without damage. absolute maximum ratings in table 10-1 are stress ratings only, and f unctional operation at the maximum is not guaranteed. stress beyond these ratings may affect device reliabi lity or cause permanent damage to the device. unless otherwise stated, all specificati ons within this chapter apply over the temperature range of -40oc to 125oc ambient temperature over the following supply ranges: v ss =v ssa =0v,v dd =v dda = 3.0?3.6v, cl < 50pf, f op = 32mhz caution this device contains protective circuitry to guard against damage due to high static voltage or electrical fields. however, normal precautions are advised to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level.
56f8023 data sheet, rev. 3 114 freescale semiconductor preliminary default mode pin group 1: gpio, tdi, tdo, tms, tck pin group 2: reset , gpioa7 pin group 3: adc and comparator analog inputs pin group 4: xtal, extal 10.1.1 electrostatic discharge (esd) model table 10-1 absolute maximum ratings (v ss = 0v, v ssa = 0v) characteristic symbol notes min max unit supply voltage range v dd -0.3 4.0 v analog supply voltage range v dda - 0.3 4.0 v adc high voltage reference v refhx - 0.3 4.0 v voltage difference v dd to v dda v dd - 0.3 0.3 v voltage difference v ss to v ssa v ss - 0.3 0.3 v digital input voltage range v in pin groups 1, 2 - 0.3 6.0 v oscillator voltage range v osc pin group 4 - 0.4 4.0 v analog input voltage range v ina pin group 3 - 0.3 4.0 v input clamp current, per pin (v in < 0) 1 1. continuous clamp current per pin is -2.0 ma v ic ? -20.0 ma output clamp current, per pin (v o < 0) 1 v oc ? -20.0 ma output voltage range (normal push-pull mode) v out pin group 1 - 0.3 4.0 v output voltage range (open drain mode) v outod pin group 2 - 0.3 6.0 v ambient temperature industrial t a - 40 105 c storage temperature range (extended industrial) t stg - 55 150 c table 10-2 56f8023 esd protection characteristic min typ max unit esd for human body model (hbm) 2000 ? ? v
general characteristics 56f8023 data sheet, rev. 3 freescale semiconductor 115 preliminary 1. theta-ja determined on 2s2p test boards is frequently lowe r than would be observed in an application. determined on 2s2p thermal test board. 2. junction to ambient thermal resistance, theta-ja (r ja ), was simulated to be equivalent to the jedec specification jesd51-2 in a horizontal configuration in natural c onvection. theta-ja was also simulated on a thermal test board with two internal plan es (2s2p, where ?s? is the number of signal layers and ?p? is the number of planes) per jesd51-6 and jesd51-7. the correct name for theta-ja for forced convection or with the non-single layer boards is theta-jma. 3. junction to case thermal resistance, theta-jc (r jc ), was simulated to be equivalent to the measured values using the cold plate technique with the cold plate temperature used as the ?case? temperature. the basic cold plate measurement technique is de- scribed by mil-std 883d, method 1012.1. this is the correct ther mal metric to use to calculate thermal performance when the package is being used with a heat sink. 4. junction to board thermal resistance, theta-jb (r jb ), is a metric of the thermal resistance from the junction to the printed circuit board determined per jesd51-8. board te mperature is measured on the top surface of the board near the package. 5. thermal characterization parameter, psi-jt (y jt ), is the ?resistance? from junction to reference point thermocouple on top center of case as defined in jesd51-2. y jt is a useful value to use to estimate junction temperature in steady state customer environments. 6. junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 7. see section 12.1 for more details on thermal design considerations. esd for machine model (mm) 200 ? ? v esd for charge device model (cdm) 750 ? ? v table 10-3 lqfp package thermal characteristics 6 characteristic comments symbol value (lqfp) unit notes junction to ambient natural convection single layer board (1s) r ja 41 c/w 2 junction to ambient natural convection four layer board (2s2p) r jma 34 c/w 1, 2 junction to ambient (@200 ft/min) single layer board (1s) r jma 34 c/w 2 junction to ambient (@200 ft/min) four layer board (2s2p) r jma 29 c/w 1, 2 junction to board r jb 24 c/w 4 junction to case r jc 8c/w3 junction to package top natural convection jt 2c/w5 table 10-2 56f8023 esd protection characteristic min typ max unit
56f8023 data sheet, rev. 3 116 freescale semiconductor preliminary default mode pin group 1: gpio, tdi, tdo, tms, tck pin group 2: reset , gpioa7 pin group 3: adc and comparator analog inputs pin group 4 xtal, extal table 10-4 recommended operating conditions (v refl x = 0v, v ssa = 0v, v ss = 0v) characteristic symbol notes min typ max unit supply voltage v dd, v dda 33.33.6 v adc reference voltage high v refhx 3.0 v dda v voltage difference v dd to v dda v dd -0.1 0 0.1 v voltage difference v ss to v ssa v ss -0.1 0 0.1 v device clock frequency using relaxation oscillator using external clock source fsysclk 1 0 32 32 mhz input voltage high (digital inputs) v ih pin groups 1, 2 2.0 5.5 v input voltage low (digital inputs) v il pin groups 1, 2 -0.3 0.8 v oscillator input voltage high xtal not driven by an external clock xtal driven by an external clock source v ihosc pin group 4 v dda - 0.8 2.0 v dda + 0.3 v dda + 0.3 v oscillator input voltage low v ilosc pin group 4 -0.3 0.8 v output source current high at v oh min.) 1 when programmed for low drive strength when programmed for high drive strength 1. total chip source or sink current cannot exceed 75ma i oh pin group 1 pin group 1 ? ? -4 -8 ma output source current low (at v ol max.) 1 when programmed for low drive strength when programmed for high drive strength i ol pin groups 1, 2 pin groups 1, 2 ? ? 4 8 ma ambient operating temperature (extended industrial) t a -40 105 c flash endurance (program erase cycles) n f t a = -40c to 125c 10,000 ? cycles flash data retention t r t j <= 85c avg 15 ? years flash data retention with <100 program/erase cycles t flret t j <= 85c avg 20 ? ? years
dc electrical characteristics 56f8023 data sheet, rev. 3 freescale semiconductor 117 preliminary 10.2 dc electrical characteristics default mode pin group 1: gpio, tdi, tdo, tms, tck pin group 2: reset , gpioa7 pin group 3: adc and comparator analog inputs pin group 4: xtal, extal table 10-5 dc electr ical characteristics at recommended operating conditions characteristic symbol notes min typ max unit test conditions output voltage high v oh pin group 1 2.4 ? ? v i oh = i ohmax output voltage low v ol pin groups 1, 2 ? ? 0.4 v i ol = i olmax digital input current high (a) pull-up enabled or disabled i ih pin groups 1, 2 ? 0 +/- 2.5 av in = 2.4v to 5.5v comparator input current high i ihc pin group 3 ? 0 +/- 2 av in = v dda oscillator input current high i ihosc pin group 3 ? 0 +/- 2 av in = v dda digital input current low 1 pull-up enabled pull-up disabled 1. see figure 10-1 i il pin groups 1, 2 -15 ? -30 0 -60 +/- 2.5 av in = 0v comparator input current low i ilc pin group 3 ? 0 +/- 2 av in = 0v oscillator input current low i ilosc pin group 3 ? 0 +/- 2 av in = 0v dac output voltage range v dac internal typically v ssa + 40mv ? typically v ssa ? 40mv v? output current 1 high impedance state i oz pin groups 1, 2 ? 0 +/- 2.5 a? schmitt trigger input hysteresis v hys pin groups 1, 2 ? 0.35 ? v ? input capacitance c in ?10?pf ? output capacitance c out ?10?pf ?
56f8023 data sheet, rev. 3 118 freescale semiconductor preliminary figure 10-1 i in /i oz vs. v in (typical; pull-up disabled) table 10-6 current consumpt ion per power supply pin mode conditions typical @ 3.3v, 25c maximum@ 3.6v, 25c i dd 1 i dda i dd 1 i dda run 32mhz device clock relaxation oscillator on pll powered on continuous mac instructi ons with fetches from program flash all peripheral modules enabled. tmr and pwm using 1x clock adc/dac powered on and clocked comparator powered on 48ma 18.8ma ? ? wait 32mhz device clock relaxation oscillator on pll powered on processor core in wait state all peripheral modules enabled. tmr and pwm using 1x clock adc/dac/comparator powered off 29ma 0 a? ? stop 4mhz device clock relaxation oscillator on pll powered off processor core in stop state all peripheral module an d core clocks are off adc/dac/comparator powered off 5.4ma 0 a? ? 2.0 0.0 - 2.0 - 4.0 - 6.0 - 8.0 - 10.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 6.0 3.54.04.55.05.5 a volt
dc electrical characteristics 56f8023 data sheet, rev. 3 freescale semiconductor 119 preliminary 10.2.1 voltage regulator specifications the 56f8023 has two on-chip regulator s. one supplies the pll and relaxa tion oscillator. it has no external pins and therefore has no external characteristics which mu st be guaranteed (other than proper operation of the device). the second regulat or supplies approximately 2.5v to the 56f8023?s core logic. this regulator requires an external 4.4 f, or greater, capacitor for pr oper operation. ceramic and tantalum capacitors tend to provide better performance tolerances. the output vo ltage can be measured directly on the v cap pin. the specifications for th is regulator are shown in table 10-8 . standby > stop 100khz device clock relaxation oscillator in standby mode pll powered off processor core in stop state all peripheral module and core clocks are off adc/dac/comparator powered off voltage regulator in standby mode 290 a0 a390 a1 a powerdown device clock is off relaxation oscillator powered off pll powered off processor core in stop state all peripheral module and core clocks are off adc /dac/comparator powered off voltage regulator in standby mode 190 a0 a250 a1 a 1. no output switching all ports configured as inputs all inputs low no dc loads table 10-7 power-on rese t low-voltage parameters characteristic symbol min typ max unit low-voltage interrupt for 3.3v supply 1 1. when v dd drops below v ei3.3 , an interrupt is generated. v ei3.3 2.58 2.7 ? v low-voltage interrupt for 2.5v supply 2 2. when v dd drops below v ei32.5 , an interrupt is generated. v e12.5 ?2.15? v low-voltage interrupt recovery hysteresis v eih ?50?mv power-on reset 3 3. power-on reset occurs whenever the internally regulated 2.5v digital supply drops below 1.8v. while power is ramping up, this signal remains active for as long as the internal 2.5v is below 2.15v or the 3.3v 1/o voltage is below 2.7v, no matter how long the ramp-up rate is. the internally regulated voltage is typically 100mv less than v dd during ramp-up until 2.5v is reached, at which time it self-regulates. por ? 1.8 1.9 v table 10-6 current consumption pe r power supply pin (continued) mode conditions typical @ 3.3v, 25c maximum@ 3.6v, 25c i dd 1 i dda i dd 1 i dda
56f8023 data sheet, rev. 3 120 freescale semiconductor preliminary 10.3 ac electrical characteristics tests are conducted using the input levels specified in table 10-5 . unless otherwise specified, propagation delays are measured fr om the 50% to the 50% point, and rise and fall times are measured between the 10% and 90% points, as shown in figure 10-2 . figure 10-2 input signal measurement references figure 10-3 shows the definitions of the following signal states: ? active state, when a bus or signal is driven, and enters a low impedance state ? tri-stated, when a bus or signal is placed in a high impedance state ? data valid state, when a signal level has reached v ol or v oh ? data invalid state, when a signal level is in transition between v ol and v oh figure 10-3 signal states table 10-8. regulator parameters characteristic symbol min typical max unit short circuit current i ss ? 450 650 ma short circuit tolerance (v cap shorted to ground) t rsc ? ? 30 minutes v ih v il fall time input signal note: the midpoint is v il + (v ih ? v il )/2. midpoint1 low high 90% 50% 10% rise time data invalid state data1 data2 valid data tri-stated data3 valid data2 data3 data1 valid data active data active
flash memory characteristics 56f8023 data sheet, rev. 3 freescale semiconductor 121 preliminary 10.4 flash memory characteristics 10.5 external clock operation timing figure 10-4 external clock timing table 10-9 flash timing parameters characteristic symbol min typ max unit program time 1 1. there is additional overhead which is part of the programming sequence. see the 56f802x and 56f803x peripheral reference manual for details. t prog 20 ? 40 s erase time 2 2. specifies page erase time. there are 512 by tes per page in the program flash memory. t erase 20 ? ? ms mass erase time t me 100 ? ? ms table 10-10 external clock op eration timing requirements 1 1. parameters listed are guaranteed by design. characteristic symbol min typ max unit frequency of operation (external clock driver) 2 2. see figure 10-4 for details on using the recommended connection of an external clock driver. f osc 488mhz clock pulse width 3 3. the chip may not function if the high or low pulse width is smaller than 6.25ns. t pw 6.25 ? ? ns external clock input rise time 4 4. external clock input rise time is measured from 10% to 90%. t rise ?? 3ns external clock input fall time 5 5. external clock input fall time is measured from 90% to 10%. t fall ?? 3ns external clock v ih v il note: the midpoint is v il + (v ih ? v il )/2. 90% 50% 10% 90% 50% 10% t pw t pw t fall t rise
56f8023 data sheet, rev. 3 122 freescale semiconductor preliminary 10.6 phase locked loop timing 10.7 relaxation oscillator timing table 10-11 pll timing characteristic symbol min typ max unit external reference crystal frequency for the pll 1 1. an externally supplied reference clock should be as free as possible from any phase jitter for the pll to work correctly. the pll is optimized for 8mhz input. f osc 48?mhz internal reference relaxation oscillator frequency for the pll f rosc ?8?mhz pll output frequency 2 (24 x reference frequency) 2. the core system clock will operate at 1/6 of the pll output frequency. f op 96 192 ? mhz pll lock time 3 3. this is the time required after the pll is enabled to ensure reliable operation. t plls ?40100s accumulated jitter using an 8mhz external crystal as the pll source 4 4. this is measured on the clko signal (programmed as system cl ock) over 264 system clocks at 32mhz system clock frequency and using an 8mhz oscillator frequency. j a ? ? 0.37 % cycle-to-cycle jitter t jitterpll ?350? ps table 10-12 relaxation oscillator timing characteristic symbol minimum typical maximum unit relaxation oscillator output frequency 1 normal mode standby mode 1. output frequency after application of 8mhz trim value, at 125c. f op ? 8.05 200 ? mhz khz relaxation oscillator stabilization time 2 2. this is the time required from standby to normal mode transition. t roscs ?1 3ms cycle-to-cycle jitter. this is measured on the clko signal (programmed prescaler_clock) over 264 clocks 3 3. j a is required to meet qsci requirements. t jitterrosc ?400? ps minimum tuning step size ? .08 ? % maximum tuning step size ? 40 ? % variation over temperature -40 c to 150oc 4 4. see figure 10-5 ? +1.0 to -1.5 +3.0 to -3.0 % variation over temperature 0 c to 105oc 4 ? 0 to +1 +2.0 to -2.0 %
relaxation oscillator timing 56f8023 data sheet, rev. 3 freescale semiconductor 123 preliminary figure 10-5 relaxation oscillator temperature variation (typical) af ter trim at 125c 8.16 8.08 8 7.92 7.84 175 -25 -50 0 50 75 100 125 150 25 degrees c (junction) mhz
56f8023 data sheet, rev. 3 124 freescale semiconductor preliminary 10.8 reset, stop, wait, mode select, and interrupt timing note: all address and data buses described here are internal. figure 10-6 gpio interrupt timi ng (negative edge-sensitive) table 10-13 reset, stop, wait, mode select, and interrupt timing 1,2 1. in the formulas, t = system clock cycle and t osc = oscillator clock cycle. for an operating frequency of 32mhz, t = 31.25ns. at 8mhz (used during reset and stop modes), t = 125ns. 2. parameters listed are guaranteed by design. characteristic symbol typical min typical max unit see figure minimum reset assertion duration t ra 4t ? ns ? minimum gpio pin assertion for interrupt t iw 2t ? ns 10-6 reset deassertion to first address fetch 3 3. during power-on reset, it is possible to use the 56f8023 internal reset stretching circuitry to extend this period to 2^21t. t rda 96t osc + 64t 97t osc + 65t ns ? delay from interrupt assertion to fetch of first instruction (exiting stop) t if ?6tns? gpio pin (input) t iw
serial peripheral interface (spi) timing 56f8023 data sheet, rev. 3 freescale semiconductor 125 preliminary 10.9 serial peripheral interface (spi) timing table 10-14 spi timing 1 1. parameters listed are guaranteed by design. characteristic symbol min max unit see figure cycle time master slave t c 125 62.5 ? ? ns ns 10-7 , 10-8 , 10-9 , 10-10 enable lead time master slave t eld ? 31 ? ? ns ns 10-10 enable lag time master slave t elg ? 125 ? ? ns ns 10-10 clock (sck) high time master slave t ch 50 31 ? ? ns ns 10-7 , 10-8 , 10-9 , 10-10 clock (sck) low time master slave t cl 50 31 ? ? ns ns 10-10 data set-up time required for inputs master slave t ds 20 0 ? ? ns ns 10-7 , 10-8 , 10-9 , 10-10 data hold time required for inputs master slave t dh 0 2 ? ? ns ns 10-7 , 10-8 , 10-9 , 10-10 access time (time to data active from high-impedance state) slave t a 4.8 15 ns 10-10 disable time (hold time to high-impedance state) slave t d 3.7 15.2 ns 10-10 data valid for outputs master slave (after enable edge) t dv ? ? 4.5 20.4 ns ns 10-7 , 10-8 , 10-9 , 10-10 data invalid master slave t di 0 0 ? ? ns ns 10-7 , 10-8 , 10-9 , 10-10 rise time master slave t r ? ? 11.5 10.0 ns ns 10-7 , 10-8 , 10-9 , 10-10 fall time master slave t f ? ? 9.7 9.0 ns ns 10-7 , 10-8 , 10-9 , 10-10
56f8023 data sheet, rev. 3 126 freescale semiconductor preliminary figure 10-7 spi master timing (cpha = 0) figure 10-8 spi master timing (cpha = 1) sclk (cpol = 0) (output) sclk (cpol = 1) (output) miso (input) mosi (output) msb in bits 14?1 lsb in t f t c t cl t cl t r t r t f t ds t dh t ch t di t dv t di (ref) t r master msb out bits 14?1 master lsb out ss (input) t ch ss is held high on master t f sclk (cpol = 0) (output) sclk (cpol = 1) (output) miso (input) mosi (output) msb in bits 14?1 lsb in t r t c t cl t cl t f t ch t dv (ref) t dv t di (ref) t r t f master msb out bits 14? 1 master lsb out ss (input) t ch ss is held high on master t ds t dh t di t r t f
serial peripheral interface (spi) timing 56f8023 data sheet, rev. 3 freescale semiconductor 127 preliminary figure 10-9 spi slave timing (cpha = 0) figure 10-10 spi slave timing (cpha = 1) sclk (cpol = 0) (input) sclk (cpol = 1) (input) miso (output) mosi (input) slave msb out bits 14?1 t c t cl t cl t f t ch t di msb in bits 14?1 lsb in ss (input) t ch t dh t r t elg t eld t f slave lsb out t d t a t ds t dv t di t r sclk (cpol = 0) (input) sclk (cpol = 1) (input) miso (output) mosi (input) slave msb out bits 14?1 t c t cl t cl t ch t di msb in bits 14?1 lsb in ss (input) t ch t dh t f t r slave lsb out t d t a t eld t dv t f t r t elg t dv t ds
56f8023 data sheet, rev. 3 128 freescale semiconductor preliminary 10.10 quad timer timing figure 10-11 timer timing table 10-15 timer timing 1, 2 1. in the formulas listed, t = the clock cycle. for 32mhz operation, t = 31.25ns. 2. parameters listed are guaranteed by design. characteristic symbol min max unit see figure timer input period p in 2t + 6 ? ns 10-11 timer input high / low period p inhl 1t + 3 ? ns 10-11 timer output period p out 125 ? ns 10-11 timer output high / low period p outhl 50 ? ns 10-11 p out p outhl p outhl p in p inhl p inhl timer inputs timer outputs
serial communication interface (sci) timing 56f8023 data sheet, rev. 3 freescale semiconductor 129 preliminary 10.11 serial communication interface (sci) timing figure 10-12 rxd pulse width figure 10-13 txd pulse width table 10-16 sci timing 1 1. parameters listed are guaranteed by design. characteristic symbol min max unit see figure baud rate 2 2. f max is the frequency of operation of the system clock in mhz, which is 32mhz for the 56f8023 device. br ? (f max /16) mbps ? rxd 3 pulse width 3. the rxd pin in qsci0 is named rxd0 a nd the rxd pin in qsci1 is named rxd1. rxd pw 0.965/br 1.04/br ns 10-12 txd 4 pulse width 4. the txd pin in qsci0 is named txd0 and the txd pin in qsci1 is named txd1. txd pw 0.965/br 1.04/br ns 10-13 lin slave mode deviation of slave node clock from nominal clock rate before synchronization f tol_unsynch -14 14 % ? deviation of slave node clock relative to the master node clock after synchronization f tol_synch -2 2 % ? minimum break character length t break 13 ? master node bit periods ? 11 ? slave node bit periods ? rxd pw rxd qsci receive data pin (input) txd pw txd qsci receive data pin (input)
56f8023 data sheet, rev. 3 130 freescale semiconductor preliminary 10.12 inter-integrated circuit interface (i 2 c) timing table 10-17 i 2 c timing characteristic symbol standard mode fast mode unit minimum maximum minimum maximum scl clock frequency f scl 01000400khz hold time (repeated) start condit ion. after this period, the first clock pulse is generated. t hd; sta 4.0 ? 0.6 ? s low period of the scl clock t low 4.7 ? 1.3 ? s high period of the scl clock t high 4.0 ? 0.6 ? s set-up time for a repeated start condition t su; sta 4.7 ? 0.6 ? s data hold time for i 2 c bus devices t hd; dat 0 1 1. the master mode i 2 c deasserts ack of an address byte simultaneously with the falling edge of scl. if no slaves acknowledge this address byte, a negative hold time can result, depending on the edge rates of the sda and scl lines. 3.45 2 2. the maximum t hd; dat must be met only if the device does not stretch the low period (t low ) of the scl signal. 0 1 0.9 2 s data set-up time t su; dat 250 3 3. set-up time in slave-transmitter mode is 1 ipbus clock period, if the tx fifo is empty. ? 100 3, 4 4. a fast mode i 2 c bus device can be used in a standard mode i 2 c bus system, but the requirement t su; dat > = 250ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line t rmax + t su; dat = 1000 + 250 = 1250ns (according to the standard mode i 2 c bus specification) before the scl line is released. ?ns rise time of both sda and scl signals t r ? 1000 20 +0.1c b 5 5. c b = total capacitance of the one bus line in pf. 300 ns fall time of both sda and scl signals t f ?300 20 +0.1c b 5 300 ns set-up time for stop condition t su; sto 4.0 ? 0.6 ? s bus free time between stop and start condition t buf 4.7 ? 1.3 ? s pulse width of spikes that must be suppressed by the input filter t sp n/a n/a 0 50 ns
jtag timing 56f8023 data sheet, rev. 3 freescale semiconductor 131 preliminary figure 10-14 timing definiti on for fast and standard mode devices on the i 2 c bus 10.13 jtag timing figure 10-15 test clo ck input timing diagram table 10-18 jtag timing characteristic symbol min max unit see figure tck frequency of operation 1 1. tck frequency of operation must be less than 1/8 the processor rate. f op dc sys_clk/8 mhz 10-15 tck clock pulse width t pw 50 ? ns 10-15 tms, tdi data set-up time t ds 5?ns 10-16 tms, tdi data hold time t dh 5?ns 10-16 tck low to tdo data valid t dv ?30ns 10-16 tck low to tdo tri-state t ts ?30ns 10-16 sda scl t hd; sta t hd; dat t low t su; dat t high t su; sta sr p s s t hd; sta t sp t su; sto t buf t f t r t f t r tck (input) v m v il v m = v il + (v ih ? v il )/2 t pw 1/f op t pw v m v ih
56f8023 data sheet, rev. 3 132 freescale semiconductor preliminary figure 10-16 test access port timing diagram input data valid output data valid t ds t dh t dv t ts tck (input) tdi (input) tdo (output) tdo (output ) tms
analog-to-digital converter (adc) parameters 56f8023 data sheet, rev. 3 freescale semiconductor 133 preliminary 10.14 analog-to-digital converter (adc) parameters table 10-19 adc parameters 1 1. all measurements were made at v dd = 3.3v, v refh = 3.3v, and v refl = ground parameter symbol min typ max unit dc specifications resolution r es 12 ? 12 bits adc internal clock f adic 0.1 ? 5.33 mhz conversion range r ad v refl ?v refh v adc power-up time 2 2. includes power-up of adc and v ref t adpu ?6 13 t aic cycles 3 3. adc clock cycles recovery from auto standby t rec ?0 1 t aic cycles 3 conversion time t adc ?6 ? t aic cycles 3 sample time t ads ?1 ? t aic cycles 3 accuracy integral non-linearity 4 (full input signal range) 4. inl measured from v in = v refl to v in = v refh inl ? +/- 3 +/- 5 lsb 5 5. lsb = least significant bit = 0.806mv differential non-linearity dnl ? +/- .6 +/- 1 lsb 5 monotonicity guaranteed offset voltage internal ref v offset ? +/- 4 +/- 9 mv offset voltage external ref v offset ? +/- 6 +/- 12 mv gain error (transfer gain) e gain ? .998 to 1.002 1.01 to .99 ? adc inputs 6 (pin group 3) 6. pin groups are detailed following table 10-1 . input voltage (external reference) v adin v refl ?v refh v input voltage (internal reference) v adin v ssa ?v dda v input leakage i ia ?0 +/- 2 a v refh current i vrefh ?0 ? a input injection current 7 , per pin 7. the current that can be injected or sourced from an unselec ted adc signal input without impacting the performance of the adc. i adi ?? 3ma input capacitance c adi ? see figure 10-17 ?pf input impedance x in ? see figure 10-17 ?ohms ac specifications signal-to-noise ratio snr 60 65 db total harmonic distortion thd 60 64 db spurious free dynamic range sfdr 61 66 db signal-to-noise plus distortion sinad 58 62 db effective number of bits enob ? 10.0 bits
56f8023 data sheet, rev. 3 134 freescale semiconductor preliminary 10.15 equivalent circuit for adc inputs figure 10-17 illustrates the adc input circ uit during sample and hold. s1 and s2 are always open/closed at the same time that s3 is closed/open. when s1/s 2 are closed and s3 is ope n, one input of the sample and hold circuit moves to (v refhx - v reflx ) / 2, while the other charges to the anal og input voltage. when the switches are flipped, the charge on c1 and c2 are averaged via s3, with the result that a single-ended analog input is switched to a differential vol tage centered about (v refhx -v reflx ) / 2. the switches switch on every cycle of the adc clock ( open one-half adc clock, cl osed one-half adc cloc k). note that there are additional capacitances associated with the analog input pad, routing, etc., but these do not filter into the s/h output voltage, as s1 provides is olation during the charge-sharing phase. one aspect of this circuit is that there is an on-going input current, which is a function of the analog input voltage, v ref , and the adc clock frequency. 1. parasitic capacitance due to package, pin- to-pin and pin-to-package base coupling; 1.8pf 2. parasitic capacitance due to the chip bond pad, esd protection devices and signal routing; 2.04pf 3. equivalent resistance for the channel select mux; 100 ohms 4. sampling capacitor at the sample and hold circuit. capaci tor c1 is normally disconnected from the input and is only connected to it at sampling time; 1.4pf figure 10-17 equivalent ci rcuit for a/d loading 10.16 comparator (cmp) parameters table 10-20 cmp parameters characteristic conditions/co mments symbol min typ max unit input offset voltage 1 1. no guaranteed specification within 0.1v of v dda or v ssa within range of v dda - .1v to v ssa + .1v v offset ? +/- 10 +/- 20 mv input propagation delay t pd ?3545ns power-up time t cpu ?tbdtbd 1 2 3 analog input 4 s1 s2 s3 c1 c2 s/h c1 = c2 = 1pf (v refhx - v reflx ) / 2 125 esd resistor 8pf noise damping capacitor
digital-to-analog converter (dac) parameters 56f8023 data sheet, rev. 3 freescale semiconductor 135 preliminary 10.17 digital-to-analog converter (dac) parameters table 10-21 dac parameters parameter conditions/comm ents symbol min typ max unit dc specifications resolution 12 12 bits conversion time tbd ? 2 s conversion rate tbd ? 500.000 conv/sec power-up time time from release of pwrdwn signal until dacout signal is valid t dapu ? ? 11 s accuracy integral non-linearity 1 1. no guaranteed specification within 5% of v dda or v ssa range of input digital words: 410 to 3891 ($19a - $f33) 5% to 95% of full range inl ? +/- 3 +/- 8.0 lsb 2 2. lsb = 0.806mv differential non-linearity 1 range of input digital words: 410 to 3891 ($19a - $f33) 5% to 95% of full range dnl ? +/- .8 < - 1 lsb 2 monotonicity > 6 si gma monotonicity, < 3.4 ppm non-monotonicity guaranteed ? offset error 1 range of input digital words: 410 to 3891 ($19a - $f33) 5% to 95% of full range v offset ? +/- 25 +/- 40 mv gain error 1 range of input digital words: 410 to 3891 ($19a - $f33) 5% to 95% of full range e gain ? +/- .5 +/- 1.5 % dac output output voltage range within 40mv of either v reflx or v refhx v out v reflx +.04v ?v refhx - .04v v ac specifications signal-to-noise ratio snr ? tbd ? db spurious free dynamic range sfdr ? tbd ? db effective number of bits enob 9 ? ? bits
56f8023 data sheet, rev. 3 136 freescale semiconductor preliminary 10.18 power consumption see section 10.1 for a list of idd requirements for the 56f8023. this section provides additional detail which can be used to optimize power consumption for a given application. power consumption is given by the following equation: a, the internal [static component], is comprised of the dc bias currents for the oscillator, leakage currents, pll, and voltage referen ces. these sources operate independent ly of processor state or operating frequency. b, the internal [state-dependent component], re flects the supply current required by certain on-chip resources only when those resources are in use. these include ram, flash memory and the adcs. c, the internal [dynamic component], is classic c*v 2 *f cmos power dissipation corresponding to the 56800e core and standard cell logic. d, the external [dynamic component], reflects power dissipated on-chip as a result of capacitive loading on the external pins of the chip. this is also commonly described as c*v 2 *f, although simulations on two of the i/o cell types used on the 56800e reveal that the power-versus-load curv e does have a non-zero y-intercept. power due to capacitive loading on output pins is (first order) a f unction of the capacitive load and frequency at which the outputs change. table 10-22 provides coefficients for calculating power dissipated in the i/o cells as a function of capacitive load. in these cases: totalpower = ((intercept + slope*cload)*frequency/10mhz) where: ? summation is performed over all ou tput pins with capacitive loads ? totalpower is expressed in mw ? cload is expressed in pf total power = a: interna l [static component] +b: internal [state-d ependent component] +c: internal [dynamic component] +d: external [dynamic component] +e: external [static component] table 10-22 i/o loading coefficients at 10mhz intercept slope 8ma drive 1.3 0.11mw / pf 4ma drive 1.15mw 0.11mw / pf
power consumption 56f8023 data sheet, rev. 3 freescale semiconductor 137 preliminary because of the low duty cycle on most device pins , power dissipation due to capacitive loads was found to be fairly low when averaged over a period of time. e, the external [static component], reflects the effects of placing resistive load s on the outputs of the device. sum the total of all v 2 /r or iv to arrive at the resistive load contribution to power. assume v = 0.5 for the purposes of these rough calculations. for instance, if there is a total of eight pwm outputs driving 10ma into leds, then p = 8*.5*.01 = 40mw. in previous discussions, power consum ption due to parasitics associated with pure input pins is ignored, as it is assumed to be negligible.
56f8023 data sheet, rev. 3 138 freescale semiconductor preliminary part 11 packaging 11.1 56f8023 package an d pin-out information this section contains package and pin-out inform ation for the 56f8023. this de vice comes in a 32-pin low-profile quad flat pack (lqfp). figure 11-1 shows the package outline, figure 11-2 shows the mechanical parameters and table 11-1 lists the pin-out. figure 11-1 top view, 56f 8023 32-pin lqfp package orientation mark pin 9 pin 25 pin 17 pin 1 gpiob6 / rxd0 / sda / clkin gpiob1 / ss0 / sda gpiob7 / txd0 / scl gpiob5 / ta1 / fault3 / clkin gpioc4 / anb0 & cmpbi3 gpioc5 / anb1 gpioc6 / anb2 / v refhb v dda v ssa gpioc2 / ana2 / v refha gpioc1 / ana1 gpioc0 / ana0 & cmpai3 v ss tck / gpiod2 reset / gpioa7 gpiob3 / mosi0 / ta3 / psrc1 gpioa3 / pwm3 gpioa2 / pwm2 gpiob0 / sclk0 / scl gpioa5 / pwm5 / ta3 / faulta2 gpiob4 / ta0 / clko / psrc2 gpioa6 / fault0 / ta0 gpiob2 / miso0 / ta2 / psrc0 tdo / gpiod1 tms / gpiod3 tdi / gpiod0 gpioa0 / pwm0 gpioa1 / pwm1 v ss v dd v cap gpioa4 / pwm4 / ta2 / fault1
56f8023 package and pin-out information 56f8023 data sheet, rev. 3 freescale semiconductor 139 preliminary table 11-1 56f8023 32-pin lqfp package identifi cation by pin number 1 1. alternate signals are in italic pin # signal name pin # signal name pin # signal name pin # signal name 1 gpiob6 rxd0 / sda / clkin 9 v ssa 17 gpiob2 miso0 / ta2 / psrc0 25 v cap 2 gpiob1 ss0 / sda 10 gpioc2 ana2 / v refha 18 gpioa6 fault0 / ta0 26 v dd 3 gpiob7 txd0 / scl 11 gpioc1 ana1 19 gpiob4 ta0 / clko / psrc2 27 v ss 4 gpiob5 ta1 / fault3 / clkin 12 gpioc0 ana0 & cmpai3 20 gpioa5 pwm5 / ta3 / fault2 28 gpioa1 pwm1 5 gpioc4 anb0 & cmpbi3 13 v ss 21 gpiob0 sclk0 / scl 29 gpioa0 pwm0 6 gpioc5 anb1 14 tci gpiod2 22 gpioa4 pwm4 / ta2 / fault1 30 tdi gpiod0 7 gpioc6 anb2 / v refhb 15 reset gpioa7 23 gpioa2 pwm2 31 tms gpiod3 8 v dda 16 gpiob3 mosi0 / ta3 / psrc1 24 gpioa3 pwm3 32 tdo gpiod1
56f8023 data sheet, rev. 3 140 freescale semiconductor preliminary figure 11-2 56f8023 32- pin lqfp mechanical information please see www.freescale.com for the most current case outline. detail y a s1 v b 1 8 9 17 25 32 ae ae p detail y base n j d f metal section ae?ae g seating plane r q w k x 0.250 (0.010) gauge plane e c h detail ad notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. datum plane ?ab? is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. datums ?t?, ?u?, and ?z? to be determined at datum plane ?ab?. 5. dimensions s and v to be determined at seating plane ?ac?. 6. dimensions a and b do not include mold protrusion. allowable protrusion is 0.250 (0.010) per side. dimensions a and b do include mold mismatch and are determined at datum plane ?ab?. 7. dimension d does not include dambar protrusion. dambar protrusion shall not cause the d dimension to exceed 0.520 (0.020). 8. minimum solder plate thickness shall be 0.0076 (0.0003). 9. exact shape of each corner may vary from depiction. dim a min max min max inches 7.000 bsc 0.276 bsc millimeters b 7.000 bsc 0.276 bsc c 1.400 1.600 0.055 0.063 d 0.300 0.450 0.012 0.018 e 1.350 1.450 0.053 0.057 f 0.300 0.400 0.012 0.016 g 0.800 bsc 0.031 bsc h 0.050 0.150 0.002 0.006 j 0.090 0.200 0.004 0.008 k 0.500 0.700 0.020 0.028 m 12 ref 12 ref n 0.090 0.160 0.004 0.006 p 0.400 bsc 0.016 bsc q 1 5 1 5 r 0.150 0.250 0.006 0.010 v 9.000 bsc 0.354 bsc v1 4.500 bsc 0.177 bsc detail ad a1 b1 v1 4x s 4x b1 3.500 bsc 0.138 bsc a1 3.500 bsc 0.138 bsc s 9.000 bsc 0.354 bsc s1 4.500 bsc 0.177 bsc w 0.200 ref 0.008 ref x 1.000 ref 0.039 ref 9 ?t? ?z? ?u? t?u 0.20 (0.008) z ac t?u 0.20 (0.008) z ab 0.10 (0.004) ac ?ac? ?ab? m 8x ?t?, ?u?, ?z? t?u m 0.20 (0.008) z ac
thermal design considerations 56f8023 data sheet, rev. 3 freescale semiconductor 141 preliminary part 12 design considerations 12.1 thermal desi gn considerations an estimation of the chip junction temperature, t j , can be obtained from the equation: t j = t a + (r j x p d ) where: the junction-to-ambient thermal resi stance is an industry-standard va lue that provides a quick and easy estimation of thermal perf ormance. unfortunately, there are two values in common usage: the value determined on a single-layer board and the value obtained on a board wi th two planes. for packages such as the pbga, these values can be different by a factor of two. which value is closer to the application depends on the power dissipated by other components on the board. th e value obtained on a single layer board is appropriate for the tightly packed printed circuit board. the va lue obtained on the board with the internal planes is usually appropriate if the board has low-power dissipation and the components are well separated. when a heat sink is used, the thermal resistance is expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance: r ja = r jc + r ca where: r jc is device related and ca nnot be influenced by the user. the user controls the thermal e nvironment to change the case to ambient thermal resistance, r ca . for instance, the user can change the size of the heat sink, the air flow around the device, the interface mate rial, the mounting arrange ment on printed circuit board, or change the thermal dissipation on th e printed circuit board surrounding the device. to determine the junction temperature of the device in the application when heat sinks are not used, the thermal characterization parameter ( jt ) can be used to determine th e junction temperature with a measurement of the temperature at the top center of the package case using the following equation: t j = t t + ( jt x p d ) where: t a = ambient temperature for the package ( o c) r j = junction-to-ambient thermal resistance ( o c/w) p d = power dissipation in the package (w) r ja = package junction-to-ambient thermal resistance (c/w) r jc = package junction-to-case thermal resistance (c/w) r ca = package case-to-ambient thermal resistance (c/w) t t = thermocouple temperature on top of package ( o c) jt = thermal characterization parameter ( o c/w) p d = power dissipation in package (w)
56f8023 data sheet, rev. 3 142 freescale semiconductor preliminary the thermal characterization parameter is measured per jesd51-2 specification using a 40-gauge type t thermocouple epoxied to the top ce nter of the package case. the th ermocouple should be positioned so that the thermocouple junction re sts on the package. a small amount of epoxy is placed over the thermocouple junction and over about 1mm of wire extending from the junction. the thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire. when heat sink is used, the junction temperature is determined from a ther mocouple inserted at the interface between the case of the p ackage and the interface material. a clearance slot or hole is normally required in the heat sink. minimizing the size of the clearan ce is important to mi nimize the change in thermal performance caused by removing part of the thermal interface to the heat sink. because of the experimental difficulties with th is technique, many engine ers measure the heat si nk temperature and then back-calculate the case temperatur e using a separate measurement of the thermal resistance of the interface. from this case temperat ure, the junction temperature is de termined from th e junction-to-case thermal resistance. 12.2 electrical design considerations use the following list of considerations to assure correct operation of the 56f8023: ? provide a low-impedance path from the board power supply to each v dd pin on the 56f8023 and from the board ground to each v ss (gnd) pin ? the minimum bypass requirement is to place 0.01?0.1f capacitors pos itioned as close as possible to the package supply pins. the recommended bypass configura tion is to place one bypass capacitor on each of the v dd /v ss pairs, including v dda /v ssa. ceramic and tantalum capacito rs tend to provide better tolerances. ? ensure that capacitor leads and associated prin ted circuit traces that connect to the chip v dd and v ss (gnd) pins are as short as possible ? bypass the v dd and v ss with approximately 100f, plus the number of 0.1f ceramic capacitors ? pcb trace lengths should be mini mal for high-frequency signals ? consider all device loads as well as parasitic capacitance due to pcb traces when calculating capacitance. this is especially critical in system s with higher capacitive loads that co uld create higher transient currents in the v dd and v ss circuits. caution this device contains protective circuitry to guard against damage due to high static voltage or electrical fields. however, normal precautions are advised to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level.
electrical design considerations 56f8023 data sheet, rev. 3 freescale semiconductor 143 preliminary ? take special care to minimize noise levels on the v ref , v dda , and v ssa pins ? using separate power planes for v dd and v dda and separate ground planes for v ss and v ssa are recommended. connect the separate analog and digital power and ground planes as close as possible to power supply outputs. if both analog circuit and dig ital circuit are powered by the same power supply, it is advisable to connect a small inductor or ferrite bead in serial with both v dda and v ssa traces. ? it is highly desirable to physically separate analog components from noisy digital components by ground planes. do not place an analog trace in parallel with digital traces. it is also desirable to place an analog ground trace around an analog signal trace to isolate it from digital traces. ? because the flash memory is programmed th rough the jtag/eonce port, qspi, qsci, or i 2 c, the designer should provide an interface to this po rt if in-circuit flash programming is desired. ? if desired, connect an exte rnal rc circuit to the r es et pin. the resistor value should be in the range of 4.7k?10k; the capacitor value should be in the range of 0.22f - 4.7f. ? add a 3.3k external pull-up on the tms pin of the jt ag port to keep eonce in a restate during normal operation if jtag converter is not present. ? during reset and after reset but before i/o initialization, all i/o pins are at input state with internal pull-up enable. the typical value of internal pull-up is aro und 110k. these internal pull-ups can be disabled by software. ? to eliminate pcb trace impedance effect, each adc input should have a 33pf-10 ohm rc filter. ? device gpios have only a down (substrate) diode on the gpio circuit. devices do not have a positive clamp diode because gpios use a floating gate structure to tolerate 5v input. th e absolute maximum clamp current is -20ma at v in less than 0v. the continuous clamp current is -2ma at v in less than 0v. if positive voltage spikes are a concern, a positive clamp is recommended. part 13 ordering information table 13-1 lists the pertinent information needed to pl ace an order. consult a freescale semiconductor sales office or authorized di stributor to determine availability and to order devices. * this package is rohs compliant. table 13-1 56f8023 ordering information device supply voltage package type pin count frequency (mhz) ambient temperature range order number mc56f8023 3.0?3.6 v low-profile quad flat pack (lqfp) 32 32 -40 to + 105 c mc56f8023vlc*
56f8023 data sheet, rev. 3 144 freescale semiconductor preliminary part 14 appendix register acronyms are revised from previous device data sheets to pr ovide a cleaner register description. a cross reference to legacy and revised acronyms are provided in the following table. note: this table comprises all peripherals used in the 56 f803x and 56f802x family; some of the peripherals described here may not be present on this device. table 14-1 legacy a nd revised acronyms register name peripheral reference manual data sheet processor expert acronym memory address new acronym legacy acronym new acronym legacy acronym start end analog-to-digital converter (adc) module contr ol 1 regi ste r ctrl1 adcr1 adc_ctrl1 adc_adcr1 adc_adcr1 0x f080 control 2 register ctrl2 adcr2 adc_ctrl2 adc_adcr2 adc_adcr2 0xf081 zero crossing control register zxctrl adzcc adc_zxctrl adc_adzcc adc_adzcc 0x f082 channel list 1 register clist1 adlst1 adc_clist1 adc_adlst1 adc_adlst1 0xf083 channel list 2 register clist2 adlst2 adc_clist2 adc_adlst2 adc_adlst2 0x f084 channel list 3 register clist3 adc_clist3 adc_adclst3 adc_adclst3 0xf085 channel list 4 register clist4 adc_clist4 adc_adclst4 adc_adclst4 0x f086 sample disable register sdis adsdis adc_sdis adc_adsdis adc_adsdis 0xf087 status regi s ter stat adstat adc_stat adc_adstat adc_adstat 0x f088 conversion ready register rdy adc_cnrdy adc_adcnrdy adc_adcnrdy 0xf089 limit status register limstat adlstat adc_limstat adc_adlstat adc_adlstat 0xf08a zero crossing status register zxstat adzcstat adc_zxstat adc_adzcstat adc_adzcstat 0xf08b res ul t 0-7 r egis ter s rslt0-7 adrslt0-7 adc_rslt0-7 adc_adrslt0-7 adc_adrslt0-7 0 xf 08c 0xf09 3 result 8-15 registers rslt8-15 adc_rslt8-15 adc_adrslt8-15 adc_adrslt8-15 0xf094 0xf09b low limit 0-7 registers lolim0-7 adllmt0-7 adc_lolim0-7 adc_adllmt0-7 adc_adllmt0-7 0x f 09c 0x f0a 3 high limit 0-7 registers hilim0-7 adhlmt0-7 adc_hilim0-7 adc_adhlmt0-7 adc_adhlmt0-7 0xf0a4 0xf0ab offset 0-7 registers offst0-7 adofs0-7 adc_offst0-7 adc_adofs0-7 adc_adofs0-7 0xf0ac 0xf0b3 power control register pwr adpower adc_pwr adc_adpower adc_adpower 0xf0b4 cal i brati on regi s ter cal adc_cal adc_adcal adc_adcal 0xf0b5
electrical design considerations 56f8023 data sheet, rev. 3 freescale semiconductor 145 preliminary computer operating properly (cop) module contr ol regi ster ctrl copctl cop_ctrl copctl copctl 0x f12 0 timeout register tout copto cop_tout copto copto 0xf121 coun ter reg is ter cntr copctr cop_cntr copctr copctr 0x f12 2 table 14-1 legacy and revi sed acronyms (continued) register name peripheral reference manual data sheet processor expert acronym memory address new acronym legacy acronym new acronym legacy acronym start end
56f8023 data sheet, rev. 3 146 freescale semiconductor preliminary inter-integrated circuit interface (i 2 c) module contr ol regi ster ctrl ibcr i2c_ctrl i2c_ibcr i2c_ibcr 0x f280 target address register tar i2c_tar i2ctar i2c_tar 0xf282 slave address register sar i2c_sar i2csar i2c_sar 0x f242 data buffer & command register data i2c_data i2c_datacmd i2c_datacmd 0xf288 standard speed clock scl high count register sshcnt i2c_ss_scl_hcnt i2c_ss_sclhcnt i2c_ss_sclhcnt 0xf 28a standard speed clock scl low count register sslcnt i2c_ss_scl_lcnt i2c_ss_scllcnt i2c_ss_scllcnt 0xf28c fast speed clock scl high count register fshcnt i2c_fs_scl_hcnt i2c_fs_sclhcnt i2c_fs_sclhcnt 0xf 28e fast speed clock scl low count register fslcnt i2c_fs_scl_lcnt i2c_fs_scllcnt i2c_fs_scllcnt 0xf290 interrupt status register istat i2c_intr_stat i2c_intrstat i2c_intrstat 0x f296 interrupt mask register ienbl i2c_intr_mask i2c_intrmask i2c_intrmask 0xf298 raw interrupt status register ristat i2c_raw_intr_ stat i2c_raw_intrstat i2c_raw_intrstat 0xf 29a receive fifo threshold level register rxft i2c_rxtl i2c_rxtl 0x f29c transmit fifo threshold level register txft i2c_txtl i2c_txtl 0xf29e clear combined & individual interrupts register clrint i2c_clrintr i2c_clrintr 0xf 2a 0 clear receive under interrupt register clrrxund i2c_clr_rxunder i2c_clr_rxunder 0xf2a2 clear receive over interrupt register clrrxovr i2c_clrover i2c_clrover 0xf 2a4 clear transmit over register clrtxovr i2c_clr_txover i2c_clr_txover 0xf2a6 clear read required interrupt register clrrdreq i2c_clr_rdreq i2c_clr_rdreq 0xf 2a8 clear transmit abort interrupt register clrtxabrt i2c_clr_txabrt i2c_clr_txabrt 0xf2aa table 14-1 legacy and revi sed acronyms (continued) register name peripheral reference manual data sheet processor expert acronym memory address new acronym legacy acronym new acronym legacy acronym start end
electrical design considerations 56f8023 data sheet, rev. 3 freescale semiconductor 147 preliminary clear receive done interrupt register clrrxdone i2c_clr_rxdone i2c_clr_rxdone 0xf 2a c clear activity interrupt register clract i2c_clractivity i2c_clractivity 0xf2ae clear stop detect interrupt register clrstpdet i2c_clr_stopdet i2c_clr_stopdet 0xf 2b0 clear start detect interrupt register clrstdet i2c_clr_star_det i2c_clr_star_det 0xf2b2 clear general call interrupt register clrgc i2c_clr_gencall i2c_clr_gencall 0xf 2b4 enable register enbl i2c_enable i2c_enable 0xf2b6 status register stat i2c_stat i2c_stat 0xf2b8 transmit fifo level register txflr i2c_txflr i2c_txflr 0xf2ba receive fifo level register rxflr i2c_rxflr i2c_rxflr 0xf 2b c transmit abort source register txabrtsrc i2c_tx_abrtsrc i2c_tx_abrtsrc 0xf2c0 component parameter 1 register comparm1 i2c_comparm1 i2c_comparm1 0x f2f a component parameter 2 register comparm2 i2c_comparm2 i2c_comparm2 0xf2fb component version 1 register comver1 i2c_comver1 i2c_comver1 0x f 2fc component version 2 register comver2 i2c_comver2 i2c_comver2 0xf2fd component type 1 register comtyp1 i2c_comtyp1 i2c_comtyp1 0x f2f e component type 2 register comtyp2 i2c_comtyp2 i2c_comtyp2 0xf2ff on-clock chip synthesis (occs) module control register ctrl pllcr occs_ctrl pllcr pllcr 0xf130 divide-by register divby plldb occs_divby plldb plldb 0xf131 status register stat pllsr occs_stat pllsr pllsr 0xf132 oscillator control register octrl osctl occs_octrl osctl osctl 0xf135 cl oc k ch eck regi s ter clkchk occs_clchk pllclchk occs_clchk 0x f136 protection register prot occs_prot pllprot occs_prot 0xf137 clock divider register clkdiv fmclkd fm_clkdiv fmclkd fmclkd 0xf400 configuration register cnfg fmcr fm_cnfg fmcr fmcr 0xf401 security high half register sechi fmsech fm_sechi fmsech fmsech 0x f403 table 14-1 legacy and revi sed acronyms (continued) register name peripheral reference manual data sheet processor expert acronym memory address new acronym legacy acronym new acronym legacy acronym start end
56f8023 data sheet, rev. 3 148 freescale semiconductor preliminary security low half register seclo fmsecl fm_seclo fmsecl fmsecl 0xf404 protection register prot fmprot fm_prot fmprot fmprot 0xf410 user status register ustat fmustat fm_ustat fmustat fmustat 0xf413 comman d regi ster cmd fmcmd fm_cmd fmcmd fmcmd 0x f414 data buffer register data fmdata fm_data fmdata fmdata 0xf418 info optional data 1 register opt1 fmopt1 fm_opt1 fmopt1 fmopt1 0 xf 4 1 b test array signature register tstsig fmtst_sig fm_tstsig fmtst_sig fmtst_sig 0xf41d general purpose input/output (gpio) module x = a ( n =0) b ( n =1) c ( n =2) d ( n =3) pull-up enable register pupen pur gpio x _pupen gpio x _pur gpio_ x _pur 0 x f 1 n 0 data register data dr gpio x _data gpio x _dr gpio_ x _dr 0xf1 n 1 data direction register ddir ddr gpio x _ddir gpio x _ddr gpio_ x _ddr 0 xf 1 n 2 peripheral enable register peren per gpio x _peren gpio x _per gpio_ x _per 0xf1 n 3 interrupt assert register iassrt iar gpio x _iassrt gpio x _iar gpio_ x _iar 0 xf 1 n 4 interrupt enable register ien ienr gpio x _ien gpio x _ienr gpio_ x _ienr 0xf1 n 5 interrupt polarity register ipol ipolr gpio x _ipol gpio x _ipolr gpio_ x _ipolr 0 x f 1 n 6 interrupt pending register ipend ipr gpio x _ipend gpio x _ipr gpio_ x _ipr 0xf1 n 7 interrupt edge-sensitive register iedge iesr gpio x _iedge gpio x _iesr gpio_ x _iesr 0 xf 1 n 8 push-pull mode registers ppoutm ppmode gpiox_ppoutm gpio x _ppmode gpio_ x _ppmode 0xf1 n 9 raw data input register rdata rawdata gpio x _rdata gpiox_rawdata gpio_ x _rawdata 0 x f 1 n a output drive strength register drive drive gpio x _drive gpio x _drive gpio_ x _drive 0xf1 n b table 14-1 legacy and revi sed acronyms (continued) register name peripheral reference manual data sheet processor expert acronym memory address new acronym legacy acronym new acronym legacy acronym start end
electrical design considerations 56f8023 data sheet, rev. 3 freescale semiconductor 149 preliminary pulse width modulator (pwm) module control register ctrl pmctl pwm_ctrl pwm_pmctl pwm_pmctl 0xf0c0 fault control register fctrl pmfctl pwm_fctrl pwm_pmfctl pwm_pmfctl 0xf0c1 fault status/acknowledge regis. fltack pmfsa pwm_fltack pwm_pmfsa pwm_pmfsa 0 x f 0 c 2 output control register out pmout pwm_out pwm_pmout pwm_pmout 0xf0c3 coun ter reg is ter cntr pmcnt pwm_cntr pwm_pmcnt pwm_pmcnt 0x f0c4 counter modulo register cmod mcm pwm_cmod pwm_mcm pwm_mcm 0xf0c5 value 0-5 registers val0-5 pmval0-5 pwm_val0-5 pwm_pmval0-5 pwm_pmval0-5 0xf0c6 0xf0cb deadtime 0-1 registers dtim0-1 pmdeadtm0-1 pwm_dtim0-1 pwm_pmdeadtm0-1 pwm_pmdeadtm0-1 0xf0cc 0xf0cd disable mapping 1-2 registers dmap1-2 pmdismap1-2 pwm_dmap1-2 pwm_pmdismap1-2 pwm_pmdismap1-2 0 x f 0 c e 0 x f 0 c f configure register cnfg pmcfg pwm_cnfg pwm_pmcfg pwm_pmcfg 0xf0d0 channel control register cctrl pmccr pwm_cctrl pwm_pmccr pwm_pmccr 0x f0d1 port register port pmport pwm_port pwm_pmport pwm_pmport 0xf0d2 internal correction control register icctrl pmiccr pwm_icctrl pwm_pmiccr pwm_pmiccr 0x f0d3 source control register sctrl pmsrc pwm_sctrl pwm_pmsrc pwm_pmsrc 0xf0d4 synchronization window register sync pwm_sync pwm_sync pwm_sync 0 x f 0 d 5 fault filter 0-3 register ffilt0-3 pwm_ffilt0-3 pwm_ffilt0-3 pwm_ffilt0-3 0xf0d6 0xf0d9 multi-scalable controller area network (mscan) module contr ol 0 regi ste r ctrl0 can_ctrl0 canctrl0 0xf80 0 control 1 register ctrl1 can_ctrl1 canctrl1 0xf801 bus timing 0 register btr0 can_btr0 canbtr0 0xf802 bus timing 1 register btr1 can_btr1 canbtr1 0xf803 rec ei ve f la g regi ster rflg can_rflg canrflg 0x f80 4 receiver interrupt enable register rier can_rier canrier 0xf805 transmitter flag register tflg can_tflg cantflg 0x f80 6 transmitter interrupt enable register. tier can_tier cantier 0xf807 transmitter msg abort request register tarq can_tarq cantarq 0x f80 8 table 14-1 legacy and revi sed acronyms (continued) register name peripheral reference manual data sheet processor expert acronym memory address new acronym legacy acronym new acronym legacy acronym start end
56f8023 data sheet, rev. 3 150 freescale semiconductor preliminary transmitter message abort acknowledge register taak can_taak cantaak 0xf809 transmitter fifo selection register tbsel can_tbsel cantbsel 0xf80a identifier acceptance control register idac can_idac canidac 0xf80b miscellaneous register misc can_misc canmisc 0xf80d receive error register rxerr can_rxerr canrxerr 0xf80e transmit error register txerr can_txerr cantxerr 0xf 80f identifier acceptance 0-3 registers idar0-3 can_idar0-3 canidar0-3 0xf810 0xf813 identifier mask 0-3 registers idmr0-3 can_idmr0-3 canidmr0-3 0xf 814 0x f817 identifier acceptance 4-7 register idar4-7 can_idar4-7 canidar4-7 0xf818 0xf81b identifier mask 4-7 registers idmr4-7 can_idmr4-7 canidmr4-7 0 xf 81c 0 xf 81f foreground receive fifo register rxfg can_rxfg canrxfg 0xf82f 0xf820 foreground transmit fifo register txfg can_txfg cantxfg 0xf 830 0 xf 83f power supervisor (ps) module control register ctrl lvicontrol ps_ctrl lvicontrol lvictrl 0xf140 status register stat lvistatus ps_stat lvistatus lvisr 0xf141 table 14-1 legacy and revi sed acronyms (continued) register name peripheral reference manual data sheet processor expert acronym memory address new acronym legacy acronym new acronym legacy acronym start end
electrical design considerations 56f8023 data sheet, rev. 3 freescale semiconductor 151 preliminary queued serial communications interface (qsci) module n = 0, 1 baud rate register rate qsci_rate qsci_scibr 0xf2 n 0 control 1 register ctrl1 qsci_ctrl1 qsci_scicr 0xf2 n 1 contr ol 2 regi ste r ctrl2 qsci_ctrl2 qsci_scicr2 0 xf 2 n 2 status register stat qsci_stat qsci_scisr 0xf2 n 3 data register data qsci_data qsci_scidr 0xf2 n 4 queued serial peripheral interface (qspi) module status and control register sctrl qspi_sctrl qspi_spscr 0 xf 2 n 0 data size and control register dsctrl qspi_dsctrl qspi_spdsr 0xf2 n 1 data receive register drcv qspi_drcv qspi_spdrr 0 xf 2 n 2 data transmit register dxmit qspi_dxmit qspi_spdtr 0xf2 n 3 fi fo contro l re gis ter fifo qspi_fifo qspi_spfifo 0 xf 2 n 4 wait register wait qspi_wait qspi_spwait 0xf2 n 5 quad-timer (tmr) module n = 0, 1, 2, 3 compare 1 register comp1 tmrcmp1 tmr n _comp1 tmr n _cmp1 tmr n _cmp1 0 xf 0 n 0 compare 2 register comp2 tmrcmp2 tmr n _comp2 tmr n _cmp2 tmr n _cmp2 0xf0 n 1 capture register capt tmrcap tmr n _capt tmr n _cap tmr n _cap 0 xf 0 n 2 load register load tmrload tmr n _load tmr n _load tmr n _load 0xf0 n 3 hold register hold tmrhold tmr n _hold tmr n _hold tmr n _hold 0 xf 0 n 4 counter register cntr tmrcntr tmr n _cntr tmr n _cntr tmr n _cntr 0xf0 n 5 contr ol regi ster ctrl tmrctrl tmr n _ctrl tmr n _ctrl tmr n _ctrl 0 x f 0 n 6 status and control register sctrl tmrscr tmr n _sctrl tmr n _scr tmr n _scr 0xf0 n 7 comparator load 1 register cmpld1 tmrcmpld1 tmr n _cmpld1 tmr n _cmpld1 tmr n _cmpld1 0 x f 0 n 8 comparator load 2 register cmpld2 tmrcmpld2 tmr n _cmpld2 tmr n _cmpld2 tmr n _cmpld2 0xf0 n 9 comparator status/control register csctrl tmrcomscr tmr n _csctrl tmr n _comscr tmr n _comscr 0 x f 0 n a input filter register filt tmr n _filt tmr n _filt tmr n _filt 0xf0 n b enable register enbl tmr n _enbl tmr n _enbl tmr n _enbl 0xf 0 n f voltage regulator (vreg) module see sim section table 14-1 legacy and revi sed acronyms (continued) register name peripheral reference manual data sheet processor expert acronym memory address new acronym legacy acronym new acronym legacy acronym start end
56f8023 data sheet, rev. 3 152 freescale semiconductor preliminary programmable interval timer (pit) module n = 0, 1, 2 control register ctrl pit n_ ctrl pitctrl0-2 pit n_ ctrl 0 xf 1 n 0 modulo register mod pit n_ mod pitmod0-2 pit n_ mod 0xf1 n 1 counter register cntr pit n_ cntr pitcntr0-2 pit n_ cntr 0 x f 1 n 2 n = 0, 1 control register ctrl dac n _ctrl dacctrl0-2 dac n _ctrl 0 xf 1 n 0 data register data dac n _data dacdata0-2 dac n _data 0xf1 n 1 step register step dac n _step dacstep0-2 dac n _step 0 xf 1 n 2 minimum value register minval dac n _minval dacminval0-2 dac n _minval 0xf1 n 3 maximum value register maxval dac n _maxval dacmaxval0-2 dac n _maxval 0 xf 1 n 4 comparator (cmp) module a x = e b x = f contr ol regi ster ctrl cmp_ctrl cmp x _ctrl cmp x _ctrl 0 x f 1 x 0 status register stat cmp_stat cmp x _stat cmp x _stat 0xf1 x 1 filter register filt cmp_filt cmp x _filt cmp x _filt 0 x f 1 x 2 table 14-1 legacy and revi sed acronyms (continued) register name peripheral reference manual data sheet processor expert acronym memory address new acronym legacy acronym new acronym legacy acronym start end
electrical design considerations 56f8023 data sheet, rev. 3 freescale semiconductor 153 preliminary interrupt controller (itcn) module interrupt priority 0-4 registers n/a n/a itcn_ipr0-4 itcn_ipr0-4 intc_ipr0-4 0x f 060 0xf064 vector base address register n/a n/a itcn_vba itcn_vba intc_vba 0xf065 fast interrupt match 0 register n/a n/a itcn_fim0 itcn_fim0 intc_fim0 0x f06 6 fast interrupt vector address low 0 n/a n/a itcn_fival0 itcn_fival0 intc_fival0 0xf067 fast interrupt vector address high 0 n/a n/a itcn_fivah0 itcn_fivah0 intc_fivah0 0x f06 8 fast interrupt match 1 register n/a n/a itcn_fim1 itcn_fim1 intc_fim1 0xf069 fast interrupt vector address low 1 n/a n/a itcn_fival1 itcn_fival1 intc_fival1 0xf 06a fast interrupt vector address high 1 n/a n/a itcn_fivah1 itcn_fivah1 intc_fivah1 0xf06b interrupt pending 0 register n/a n/a itcn_irqp0 itcn_irqp0 intc_irqp0 0x f06c interrupt pending 1 register n/a n/a itcn_irqp1 itcn_irqp1 intc_irqp1 0xf06d interrupt pending 2 register n/a n/a itcn_irqp2 itcn_irqp2 intc_irqp2 0xf 06e system integration module (sim) control register n/a n/a sim_ctrl sim_control sim_control 0xf100 reset status register n/a n/a sim_rstat sim_rststs sim_rststs 0xf101 software control 0-3 registers n/a n/a sim_swc0-3 sim_scr0-3 sim_scr0-3 0xf 102 0x f105 most significant half jtag id n/a n/a sim_mshid sim_msh_id sim_msh_id 0xf106 least significant half jtag id n/a n/a sim_lshid sim_lsh_id sim_lsh_id 0x f107 power control register n/a n/a sim_pwr sim_power 0xf108 clock out select register n/a n/a sim_clkout sim_clkosr sim_clkosr 0xf 10a peripheral clock rate register n/a n/a sim_pcr sim_pcr sim_pcr 0xf10b peripheral clock enable 0-1 register n/a n/a sim_pce0-1 sim_pce0-1 sim_pce0-1 0 xf 1 0 c 0 x f1 0 d peripheral stop disable 0-1 register n/a n/a sim_sd0-1 sim_sd0-1 sim_sd0-1 0xf10e 0xf10f table 14-1 legacy and revi sed acronyms (continued) register name peripheral reference manual data sheet processor expert acronym memory address new acronym legacy acronym new acronym legacy acronym start end
56f8023 data sheet, rev. 3 154 freescale semiconductor preliminary i/o short address location high register n / a n / a sim_isalh sim_isalh sim_isalh 0 x f 1 1 0 i/o short address location low register n/a n/a sim_isall sim_isall sim_isall 0xf111 protection register n/a n/a sim_prot sim_prot sim_prot 0xf112 gpioa peripheral select 0 register n/a n/a sim_gpisa0 sim_gpisa0 sim_gpisa0 0xf113 gpioa peripheral select 0 register n / a n / a sim_gpsa1 sim_gpsa1 sim_gpsa1 0 x f 1 1 4 gpiob peripheral select 0 register n/a n/a sim_gpsb0 sim_gpsb0 sim_gpsb0 0xf115 gpiob peripheral select 1 register n / a n / a sim_gpsb1 sim_gpsb1 sim_gpsb1 0 x f 1 1 6 gpio perip. select register for gpio c & d n/a n/a sim_gpscd sim_gpscd sim_gpscd 0xf117 internal peripheral. select register for pwm n / a n / a sim_ispwm sim_ispwm sim_ispwm 0 x f 1 1 8 internal peripheral select register for dac n/a n/a sim_ipsdac sim_ipsdac sim_ipsdac 0xf119 internal peripheral select register for tmra n/a n/a sim_ipstmra sim_ipstmra sim_ipstmra 0xf 11a table 14-1 legacy and revi sed acronyms (continued) register name peripheral reference manual data sheet processor expert acronym memory address new acronym legacy acronym new acronym legacy acronym start end
electrical design considerations 56f8023 data sheet, rev. 3 freescale semiconductor 155 preliminary
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